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By ashokraj yellamraju
Atpg overview
• Atpg means name in the sense automatic test pattern generation, it is generating the
patterns to detect faults.
• sets of 1s and 0s placed on primary input pins during the manufacturing test process to
determine if the chip is functioning properly.
• When the test pattern is applied, the Automatic Test Equipment (ATE) determines if the
circuit is free from manufacturing defects by comparing the fault-free output.
The ATPG Process
• The goal of ATPG is to create a set of patterns that achieves a given test coverage, where
test coverage is the total percentage of testable faults the pattern set actually detects.
• 1) generating patterns
• The type of fault simulation used in random pattern test generation cannot replace
deterministic test generation because it can never identify redundant faults.
• 2) Deterministic Pattern Test Generation : An ATPG tool uses deterministic test pattern
generation when it creates a test pattern intended to detect a given fault.
• The procedure is to pick a fault from the fault list, create a pattern to detect the fault, fault
simulate the pattern, and check to make sure the pattern detects the fault.
Test types
Fault classes
• 1. Untestable (UT) :
• 1. Unused(UU)
• 2. Tied(TI)
• 3. Blocked(BL)
• 4. Redundant(RE)
• 2. Testable (TE) :
• 1. Detected (DT)
• 2. Posdet (PD)
• 3. ATPG_untestable (AU)
• 4. Undetected (UD)
1. Untestable (UT) :
1. Unused(UU):
• The tied fault class includes faults on gates circuitry at A causes tied faults at A, B, C,
and D.
where the point of the fault is tied to a value
identical to the fault stuck value. These are
possible causes of tied circuitry:
Tied signals
• The detected fault class includes all faults that the ATPG process identifies as detected.
• det_simulation (DS) - faults detected when the tool performs fault simulation(with patterns,
its done during functioning/capture mode)
• det_implication (DI) - faults detected when the tool performs learning analysis(without
patterns, its done during scan paths SI to SO)
2. Posdet (PD):
• The posdet, or possible-detected fault class includes all faults that fault simulation identifies as
possible-detected but not hard detected.
posdet_testable (PT) - potentially detectable posdet faults. PT faults result when the tool cannot
prove the 0/X or 1/X difference is the only possible outcome.
• Typically, faults may be classified as PU during ATPG or when the “compress_patterns -reset_au”
command is used.
3. ATPG_untestable (AU):
• The ATPG_untestable fault class includes all faults for which the test generator is unable to
find a pattern to create a test, and yet cannot prove the fault redundant.
• You cannot detect them by increasing the test generator abort limit.
• The tools place faults in the AU category based on the type of deterministic test generation
method used.
4. Undetected (UD):
• The undetected fault class includes undetected faults that cannot be proven untestable or
ATPG_untestable. The undetected class contains groups:
uncontrolled (UC) - undetected faults, which during pattern simulation, never achieve the
value at the point of the fault required for fault detection—that is, they are uncontrollable.
• Faults that remain UC or UO after ATPG are aborted, which means that a higher abort limit
may reduce the number of UC or UO faults.
Note: Uncontrolled and unobserved faults can be equivalent faults. If a fault is both
uncontrolled and unobserved, it is categorized as UC.
Fault Class Hierarchy
Testability Calculations
Test Coverage:
• Test coverage, which is a measure of test quality, is the percentage of faults detected from
among all testable faults.
• Typically, this is the number of most concern when you consider the testability of your design.
————————————————————x 100
#testable
• In this formula, posdet_credit is the user-selectable detection credit (the default is 50%) given to
possible detected faults with the set_possible_credit command.
Fault Coverage
• Fault coverage consists of the percentage of faults detected from among all faults that the test
pattern set tests—treating untestable faults the same as undetected faults.
—————————————————————— x 100
#full
ATPG Effectiveness:
• ATPG effectiveness measures the ATPG tool’s ability to either create a test for a fault, or prove
that a test cannot be created for the fault under the restrictions placed on the tool.
———————————————————————————x 100
#full
STUCK-AT FAULTS
Single Stuck-at Fault
• Example: NAND gate has 3 fault sites ( ) and 6 single stuck-at faults
Fault Equivalence
Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect
f2.
• If faults f1 and f2 are equivalent then the corresponding faulty functions are identical.
Fault collapsing: All single faults of a logic circuit can be divided into disjoint equivalence
subsets, where all faults in a subset are mutually equivalent.
• A collapsed fault set contains one fault from each equivalence subset.
EQUIVALENCE RULES
EQUIVALENCE COLLAPSING EXAMPLE
Faults in orange
color are by
equivalence
collapsing
EQUIVALENCE COLLAPSING ANOTHER EXAMPLE
orange
Fault Dominance:
• If all tests of some fault F1 detect another fault F2, then F2 is said to dominate F1.
Dominance fault collapsing: If fault F2 dominates F1, then F2 is removed from the fault list.
EQUIVALENCE DOMINANCE EXAMPLE
EQUIVALENCE DOMINANCE ANOTHER EXAMPLE
Select fault types/models during LABS
• set fault type Stuck (default)Fault model to be used for ATPG
• Also: Iddq, Toggle, Transition, Path_delay, Bridge
• add faults –all add faults to current fault list, discarding all patterns and setting all faults to undetected
• options for each fault model; Ex. stuck_at 01 (or 1 or 0)
• IDDQ testing equipment applies a set of patterns to the design, lets the current settle, then
measures for excessive current draw. Devices that draw excessive current may have
internal manufacturing defects.
• Because IDDQ tests do not have to propagate values to output pins, the set of test vectors
for detecting and measuring a high percentage of faults may be very compact.
• The ATPG tool efficiently creates this compact test vector set.
Stuck at example
With short
Due to short at
pmos, it results for
high input also it
1 consumes power
AT SPEED TESTING and the Transition Fault Model
• Transition faults model large delay defects • There are 2 methods used to find transition
at gate terminals in the circuit under test. delays
• The purpose of fault simulation is to determine the fault coverage of the current pattern
source for the faults in the active fault list. The purpose of “good” simulation is to verify the
simulation model.
• Typically, you use the good and fault simulation capabilities of the ATPG tool to grade
existing hand- or ATPG-generated pattern sets.