Multitasking and Task

Switching in Real Mode

Prepared By
Dipan A Parikh
Roll No. 200
 Contents
o Introduction
o Definition – Multitasking
o How Multitasking works
o Types of Multitasking
o Task structure
o Introduction to task and Task
Switch
o Task Switching
 Introduction
In multitasking, the CPU switches back and forth quickly
between programs, giving the appearance that all
programs are running simultaneously. In task switching,
the CPU does not switch back and forth, but executes
only one program at a time. Task switching does allow
you to switch smoothly from one program to another.
Task switching is sometimes called context switching
 Multitasking
 The 386, as mentioned earlier, has support for
multitasking, i.e. running several processes concurrently.
In reality, however, they do not run concurrently. It only
appears to the user as though they were all running at the
same time.
The 386 uses the Task State Segments (TSSs) to support
multitasking. The TSS descriptor points to a buffer
which must be at least 104 bytes long. In addition to
multitasking, TSSs can also be used for hardware
interrupt handling (using task gates in the IDT).
 The TSS selector is neither readable nor
writeable. Generally, a TSS alias is
created, which is nothing but a "data type“
segment pointing to the TSS buffer. TSS
selectors always appear in the GDT, never
in LDT or IDT. However, as mentioned
above, task gates may appear in the IDT.
The processor uses the TSS selector
internally.
 Since a multitasking switch requires the processor
state to be saved, the buffer mostly contains the
contents of the hardware registers. When a task
switch occurs, the processor saves various details in
the TSS buffer automatically. This process is very
quick and hence not many CPU cycles are wasted in
switching to a new task. Before a task is initially
started, the operating system has to fill in certain
entries in the TSS buffer.
 A task switch may occur during a "far jump" or a "far
call". The offset of the call or jump is simply ignored. The
values in the TSS are loaded into the registers and the
new task beings to execute. The selector referred by the
jump or call must be a TSS selector or a task gate. The
task gate contains the TSS selector. But unlike the TSS
selector, the task gate may occur in the GDT, IDT or
LDT.
 The 386 also supports nested tasks. It handles nested tasks using
the NT bit in the EFLAGS register. Whenever a task "calls"
another task, the 386 stores the old task's TSS selector in the
"back-link" field of the new TSS. Also, the NT bit in the EFLAGS
register is set. When the new task wishes to return to the old one, it
issues an IRET instruction.
 The TSS aren't reentrant. Whenever a task is running, the 386 sets
the BUSY bit in the TSS selector to indicate this. This is done to
prevent recurive calling of tasks.
 It is incorrect to say that a multitasking OS runs multiple
programs (i.e., tasks) simultaneously. In reality, it loads a
task into memory, permits it to run for a while and then
suspends it. It suspends the program by creating a snapshot,
or image, of all or many of the processor's registers in
memory. In the IA32 architecture, the image is stored in a
special data structure in memory referred to as a Task State
Segment (TSS) and is accomplished by performing an
automatic series of memory write transactions. In other
words, the exact state of the processor at the point of
suspension is saved in memory.
 Having effectively saved a snapshot that indicates the
point of suspension and the processor's complete state at
the time, the processor then initiates another task by
loading it into memory and jumping to its entry point.
Based on some OS-specific criteria, the OS at some point
makes the decision to suspend this task as well. As before,
the state of the processor is saved in memory (in this task's
TSS) as a snapshot of the task's state at its point of
suspension.
 At some point, the OS makes the decision to resume a
previously-suspended task. This is accomplished by
reloading the processor's registers from the
previously-saved register image (i.e., its TSS) by
performing a series of memory read transactions. The
processor then uses the address pointer stored in the
CS:EIP register pair to fetch the next instruction,
thereby resuming program execution at the point
where it had been suspended earlier.
 The criteria that an OS uses in making the decision to suspend a
program is specific to that OS. It may simply use timeslicing—
each program is permitted to execute for a fixed amount of time
(e.g., 10ms). At the end of that period of time, the currently
executing task is suspended and the next task in the queue is
started or resumed. The OS may assign priority levels to
programs, thereby permitting a higher priority program to
"preempt" a lower priority program that may currently be
running.
 This is referred to as preemptive multitasking. The
OS would also choose to suspend the currently
executing program if the program needs something
that is not immediately available (e.g., when it
attempts an access to a page of information that is
currently not in memory, but resides on a mass
storage device).
 TASK STRUCTURE
A task is made up of two parts: a task execution space and a task-
state segment (TSS). The task execution space consists of a code
segment, a stack segment, and one or more data segments If an
operating system or executive uses the processor’s privilege-level
protection mechanism, the task execution space also provides a
separate stack for each privilege level. The TSS specifies the
segments that make up the task execution space and provides a
storage place for task state information. In multitasking systems, the
TSS also provides a mechanism for linking tasks.
 The following items define the state of the currently executing task:
 The task’s curent execution space, defined by the segment selectors in the
segment
 registers (CS, DS, SS, ES, FS, and GS).
 The state of the general-purpose registers.
 The state of the EFLAGS register.
 The state of the EIP register.
 The state of control register CR3.
 The state of the task register.
 The state of the LDTR register.
 The I/O map base address and I/O map (contained in the TSS).
 Stack pointers to the privilege 0, 1, and 2 stacks (contained in the TSS).
 Link to previously executed task (contained in the TSS).
 Prior to dispatching a task, all of these items are contained in the task’s TSS,
except the state of the task register. Also, the complete contents of the LDTR
register are not contained in the TSS, only the segment selector for the LDT.

Software or the processor can dispatch a task for execution in one of the
following ways:
 A explicit call to a task with the CALL instruction.
 A explicit jump to a task with the JMP instruction.
 An implicit call (by the processor) to an interrupt-handler task.
 An implicit call to an exception-handler task.
 A return (initiated with an IRET instruction) when the NT flag in the
EFLAGS register is set.
When a task is dispatched for execution, a task switch automatically occurs
between the currently running task and the dispatched task. During a task
switch, the execution environment
of the currently executing task (called the task’s state or context) is saved in
its TSS and execution
of the task is suspended. The context for the dispatched task is then loaded
into the processor and execution of that task begins with the instruction
pointed to by the newly loaded EIP
register. If the task has not been run since the system was last initialized, the
EIP will point to
the first instruction of the task’s code; otherwise, it will point to the next
instruction after the last
instruction that the task executed when it was last active.
 Task Switching
The processor transfers execution to another task in any of
four cases:
 The current program, task, or procedure executes a JMP or
CALL instruction to a TSS descriptor in the GDT.
 The current program, task, or procedure executes a JMP or
CALL instruction to a task-gate descriptor in the GDT or
the current LDT.
 An interrupt or exception vector points to a task-gate
descriptor in the IDT.
 The current task executes an IRET when the NT flag in the
EFLAGS register is set.

The JMP, CALL, and IRET instructions, as well as interrupts

and exceptions, are all generalized mechanisms for
redirecting a program. The referencing of a TSS descriptor or
a task gate (when calling or jumping to a task) or the state of
the NT flag (when executing an IRET instruction) determines
whether a task switch occurs.
 The processor performs the following operations when switching to a new task:
1. Obtains the TSS segment selector for the new
task as the operand of the JMP or CALL
instruction, from a task gate, or from the
previous task link field (for a task switch initiated
with an IRET instruction).
2. Checks that the current (old) task is allowed
to switch to the new task. Data-access
privilege rules apply to JMP and CALL
instructions.
The CPL of the current (old) task and the RPL of the
segment selector for the new task must be less than or
equal to the DPL of the TSS descriptor or task gate being
referenced. Exceptions, interrupts (except for interrupts
generated by the INT n instruction), and the IRET
instruction are permitted to switch tasks regardless of the
DPL of the destination task-gate or TSS descriptor. For
interrupts generated by the INT n instruction, the DPL is
checked.
3. Checks that the TSS descriptor of the new task is
marked present and has a valid limit (greater
than or equal to 67H).
4. Checks that the new task is available (call, jump,
exception, or interrupt) or busy (IRET return).
5. Checks that the current (old) TSS, new TSS, and
all segment descriptors used in the task switch
are paged into system memory.
6. If the task switch was initiated with a JMP or IRET
instruction, the processor clears the busy (B) flag
in the current (old) task’s TSS descriptor; if
 initiated with a CALL instruction, an exception, or an
interrupt, the busy (B) flag is left set.

7. If the task switch was initiated with an IRET instruction,

the processor clears the NT flag in a temporarily saved
image of the EFLAGS register; if initiated with a CALL
or JMP instruction, an exception, or an interrupt, the NT
flag is left unchanged in the saved EFLAGS image.
8. Saves the state of the current (old) task in the
current task’s TSS. The processor finds the
base address of the current TSS in the task
register and then copies the states of the
following registers into the current TSS: all the
general-purpose registers, segment selectors
from the segment registers, the temporarily
saved image of the EFLAGS register, and the
instruction pointer register (EIP).
9. If the task switch was initiated with a CALL instruction, an
exception, or an interrupt, the processor will set the NT flag
in the EFLAGS loaded from the new task. If initiated with an
IRET instruction or JMP instruction, the NT flag will reflect
the state of NT in the EFLAGS loaded from the new task.
10. If the task switch was initiated with a CALL instruction,
JMP instruction, an exception, or an interrupt, the processor
sets the busy (B) flag in the new task’s TSS descriptor; if
initiated with an IRET instruction, the busy (B) flag is left set.
11. Loads the task register with the segment selector and
descriptor for the new task's TSS.
12. The TSS state is loaded into the processor. This includes
the LDTR register, the PDBR (control register CR3), the
EFLAGS registers, the EIP register, the general-purpose
registers, and the segment selectors. Note that a fault during
the load of this state may corrupt architectural state.
13. The descriptors associated with the segment selectors are
loaded and qualified. Any errors
associated with this loading and qualification occur in the
context of the new task.
At this point, if all checks and saves have been carried out
successfully, the processor commits to the task switch. If an
unrecoverable error occurs in steps 1 through 11, the
processor does not complete the task switch and insures that
the processor is returned to its state prior to the execution of
the instruction that initiated the task switch. If an
unrecoverable error occurs in step 12, architectural state
may be corrupted, but an attempt will be made to handle the
error in the prior execution environment.
 If an unrecoverable error occurs after the commit point (in
step 13), the processor completes the task switch (without
performing additional access and segment availability
checks) and generates the appropriate exception prior to
beginning execution of the new task. If exceptions occur
after the commit point, the exception handler must finish the
task switch itself before allowing the processor to begin
executing the new task.
14. Begins executing the new task. (To an exception handler,
the first instruction of the new task appears not to have been
executed.)
 The state of the currently executing task is always saved
when a successful task switch occurs.
 If the task is resumed, execution starts with the instruction
pointed to by the saved EIP value, and the registers are
restored to the values they held when the task was suspended.
 When switching tasks, the privilege level of the
new task does not inherit its privilege level from
the suspended task. The new task begins executing at the
privilege level specified in the CPL field of the CS register,
which is loaded from the TSS.
THANK YOU