Introduction to

CMOS VLSI
Design

Lecture 10:
Sequential Circuits
David Harris

Harvey Mudd College

Spring 2004
 Outline
 Floorplanning
 Sequencing
 Sequencing Element Design
 Max and Min-Delay
 Clock Skew
 Time Borrowing
 Two-Phase Clocking

10: Sequential Circuits CMOS VLSI Design Slide 2

 Project Strategy
 Proposal
– Specifies inputs, outputs, relation between them
 Floorplan
– Begins with block diagram
– Annotate dimensions and location of each block
– Requires detailed paper design
 Schematic
– Make paper design simulate correctly
 Layout
– Physical design, DRC, NCC, ERC

10: Sequential Circuits CMOS VLSI Design Slide 3

 Floorplan
 How do you estimate block areas?
– Begin with block diagram
– Each block has
• Inputs
• Outputs
• Function (draw schematic)
• Type: array, datapath, random logic
 Estimation depends on type of logic

10: Sequential Circuits CMOS VLSI Design Slide 4

 MIPS Floorplan
10 I/O pads

mips
(4.6 M2)

control
1500  x 400 
(0.6 M2)
alucontrol
200  x 100 
wiring channel: 30 tracks = 240  (20 k2)
10 I/O pads

10 I/O pads
5000 

3500

1690

zipper 2700  x 250 

datapath
2700  x 1050 
(2.8 M2)

bitslice 2700  x 100 

2700 

3500 

10 I/O pads

5000

10: Sequential Circuits CMOS VLSI Design Slide 5

 Area Estimation
 Arrays:
– Layout basic cell
– Calculate core area from # of cells
– Allow area for decoders, column circuitry
 Datapaths
– Sketch slice plan
– Count area of cells from cell library
– Ensure wiring is possible
 Random logic
– Compare complexity do a design you have done

10: Sequential Circuits CMOS VLSI Design Slide 6

 MIPS Slice Plan

srcB
writedata bitlines srcA
memdata
aluresult
adr

immediate
pc
aluout
44 24 93 93 93 93 93 44 24 52 48 48 48 48 16 86 93 131 93 44 24 93 131 39 93 39 24 44 39 39 160131

and2
mux2
inv
flop
flop
flop
flop
flop
mux2
inv
writedriver
dualsram
dualsram
dualsram
dualsrambit0
srampullup
readmux
flop
mux4
flop
mux2
inv
flop
mux4
and2
flop

mux4
inv
mux2
and2
or2
fulladder
IR3...0 register file srcB srcA PC ALU
adrmux

MDR

writemux

aluout

zerodetect
ramslice

10: Sequential Circuits CMOS VLSI Design Slide 7

Typical Layout Densities
 Typical numbers of high-quality layout
 Derate by 2 for class projects to allow routing and
some sloppy layout.
 Allocate space for big wiring channels
Element Area
Random logic (2 metal layers) 1000-1500 2 / transistor
Datapath 250 – 750 2 / transistor
Or 6 WL + 360 2 / transistor
SRAM 1000 2 / bit
DRAM 100 2 / bit
ROM 100 2 / bit

10: Sequential Circuits CMOS VLSI Design Slide 8

 Sequencing
 Combinational logic
– output depends on current inputs
 Sequential logic
– output depends on current and previous inputs
– Requires separating previous, current, future
– Called state or tokens
– Ex: FSM, pipeline
clk clk clk clk

in out
CL CL CL

Finite State Machine Pipeline

10: Sequential Circuits CMOS VLSI Design Slide 9

 Sequencing Cont.
 If tokens moved through pipeline at constant speed,
no sequencing elements would be necessary
 Ex: fiber-optic cable
– Light pulses (tokens) are sent down cable
– Next pulse sent before first reaches end of cable
– No need for hardware to separate pulses
– But dispersion sets min time between pulses
 This is called wave pipelining in circuits
 In most circuits, dispersion is high
– Delay fast tokens so they don’t catch slow ones.

10: Sequential Circuits CMOS VLSI Design Slide 10

 Sequencing Overhead
 Use flip-flops to delay fast tokens so they move
through exactly one stage each cycle.
 Inevitably adds some delay to the slow tokens
 Makes circuit slower than just the logic delay
– Called sequencing overhead
 Some people call this clocking overhead
– But it applies to asynchronous circuits too
– Inevitable side effect of maintaining sequence

10: Sequential Circuits CMOS VLSI Design Slide 11

 Sequencing Elements
 Latch: Level sensitive
– a.k.a. transparent latch, D latch
 Flip-flop: edge triggered
– A.k.a. master-slave flip-flop, D flip-flop, D register
 Timing Diagrams clk clk

Latch

Flop
– Transparent
D Q D Q

– Opaque clk

– Edge-trigger
D

Q (latch)

Q (flop)

10: Sequential Circuits CMOS VLSI Design Slide 12

 Sequencing Elements
 Latch: Level sensitive
– a.k.a. transparent latch, D latch
 Flip-flop: edge triggered
– A.k.a. master-slave flip-flop, D flip-flop, D register
 Timing Diagrams clk clk

Latch

Flop
– Transparent
D Q D Q

– Opaque clk

– Edge-trigger
D

Q (latch)

Q (flop)

10: Sequential Circuits CMOS VLSI Design Slide 13

 Latch Design
 Pass Transistor Latch
 Pros 
+
+ D Q
 Cons
–
–
–
–
–
–
10: Sequential Circuits CMOS VLSI Design Slide 14
 Latch Design
 Pass Transistor Latch
 Pros 
+ Tiny
+ Low clock load D Q
 Cons
– Vt drop Used in 1970’s
– nonrestoring
– backdriving
– output noise sensitivity
– dynamic
– diffusion input
10: Sequential Circuits CMOS VLSI Design Slide 15
 Latch Design
 Transmission gate

+
- D Q

10: Sequential Circuits CMOS VLSI Design Slide 16

 Latch Design
 Transmission gate

+ No Vt drop
- Requires inverted clock D Q

10: Sequential Circuits CMOS VLSI Design Slide 17

 Latch Design
 Inverting buffer 
+ D
X
Q
+

+ Fixes either 

• D Q
•

–

10: Sequential Circuits CMOS VLSI Design Slide 18

 Latch Design
 Inverting buffer 
+ Restoring D
X
Q
+ No backdriving

+ Fixes either 

• Output noise sensitivity D Q

• Or diffusion input

– Inverted output

10: Sequential Circuits CMOS VLSI Design Slide 19

 Latch Design
 Tristate feedback

+
X
– D Q



10: Sequential Circuits CMOS VLSI Design Slide 20

 Latch Design
 Tristate feedback

+ Static
X
– Backdriving risk D Q



 Static latches are now essential



10: Sequential Circuits CMOS VLSI Design Slide 21

 Latch Design
 Buffered input

+ X
D Q
+ 


10: Sequential Circuits CMOS VLSI Design Slide 22

 Latch Design
 Buffered input

+ Fixes diffusion input X
D Q
+ Noninverting 


10: Sequential Circuits CMOS VLSI Design Slide 23

 Latch Design
 Buffered output  Q

+ D
X




10: Sequential Circuits CMOS VLSI Design Slide 24

 Latch Design
 Buffered output  Q

+ No backdriving D
X




 Widely used in standard cells 

+ Very robust (most important)
- Rather large
- Rather slow (1.5 – 2 FO4 delays)
- High clock loading

10: Sequential Circuits CMOS VLSI Design Slide 25

 Latch Design
 Datapath latch Q

+ X
D
-



10: Sequential Circuits CMOS VLSI Design Slide 26

 Latch Design
 Datapath latch Q

+ Smaller, faster X
D
- unbuffered input



10: Sequential Circuits CMOS VLSI Design Slide 27

 Flip-Flop Design
 Flip-flop is built as pair of back-to-back latches
 
X
D Q

 

  Q

X
D Q
 
 

 

10: Sequential Circuits CMOS VLSI Design Slide 28

 Enable
 Enable: ignore clock when en = 0
– Mux: increase latch D-Q delay
– Clock Gating: increase en setup time, skew
Symbol Multiplexer Design Clock Gating Design
 en

 

D 1
Latch

Latch

Latch
D Q Q D Q
0

en en

 en


 D 1
Flop

Q
0 Flop
Flop

D Q D Q
en
en

10: Sequential Circuits CMOS VLSI Design Slide 29

 Reset
 Force output low when reset asserted
 Synchronous vs. asynchronous
 
Symbol

Latch

Flop
D Q D Q

reset reset
Synchronous Reset

 Q   Q

reset reset
Q
D D
 

  

 


Q
Q 
Asynchronous Reset

 
reset
reset
D
D 
 

 
reset
reset




10: Sequential Circuits CMOS VLSI Design Slide 30

 Set / Reset
 Set forces output high when enabled

 Flip-flop with asynchronous set and reset



reset
set Q
D




set
reset



10: Sequential Circuits CMOS VLSI Design Slide 31

 Sequencing Methods
Tc

 Flip-flops

Flip-Flops
clk

 2-Phase Latches clk clk

 Pulsed Latches

Flop

Flop
Combinational Logic

2-Phase Transparent Latches

1
tnonoverlap tnonoverlap
Tc/2
2

1 2 1

Latch

Latch
Latch
Combinational Combinational
Logic Logic
Half-Cycle 1 Half-Cycle 1
Pulsed Latches

p tpw

p p

Latch
Latch

Combinational Logic

10: Sequential Circuits CMOS VLSI Design Slide 32

 Timing Diagrams
Contamination and
Propagation Delays A tpd
Combinational
A Y
tpd Logic Prop. Delay Logic
Y tcd

tcd Logic Cont. Delay

clk clk tsetup
thold
tpcq Latch/Flop Clk-Q Prop Delay

Flop
D Q D

tccq Latch/Flop Clk-Q Cont. Delay tpcq

Q tccq

tpdq Latch D-Q Prop Delay

clk tsetup thold
clk
tpcq Latch D-Q Cont. Delay Latch
tccq tpcq

D Q D tpdq
tsetup Latch/Flop Setup Time tcdq
Q

thold Latch/Flop Hold Time

10: Sequential Circuits CMOS VLSI Design Slide 33
 Max-Delay: Flip-Flops
t pd  Tc    clk clk
     Q1 D2
Combinational Logic

F1

F2
sequencing overhead

Tc

tsetup
clk
tpcq

Q1 tpd

D2

10: Sequential Circuits CMOS VLSI Design Slide 34

 Max-Delay: Flip-Flops
t pd  Tc   tsetup  t pcq 
clk clk

     Q1 D2
Combinational Logic

F1

F2
sequencing overhead

Tc

tsetup
clk
tpcq

Q1 tpd

D2

10: Sequential Circuits CMOS VLSI Design Slide 35

Max Delay: 2-Phase Latches
1 2 1
t pd  t pd 1  t pd 2  Tc    D1 Q1 D2 Q2 D3 Q3
     Combinational Combinational

L1

L2

L3
sequencing overhead Logic 1 Logic 2

1

2
Tc

D1 tpdq1

Q1 tpd1

D2 tpdq2

Q2 tpd2

D3

10: Sequential Circuits CMOS VLSI Design Slide 36

Max Delay: 2-Phase Latches
1 2 1
t pd  t pd 1  t pd 2  Tc  2t  
pdq D1 Q1 Combinational D2 Q2 Combinational D3 Q3

L1

L2

L3
sequencing overhead Logic 1 Logic 2

1

2
Tc

D1 tpdq1

Q1 tpd1

D2 tpdq2

Q2 tpd2

D3

10: Sequential Circuits CMOS VLSI Design Slide 37

Max Delay: Pulsed Latches
t pd  Tc  max   p p

         D1 Q1
Combinational Logic
D2 Q2

L1

L2
sequencing overhead

Tc

D1 tpdq

(a) tpw > tsetup

Q1 tpd

D2

p

tpcq Tc tpw
Q1 tpd tsetup
(b) tpw < tsetup
D2

10: Sequential Circuits CMOS VLSI Design Slide 38

 Max Delay: Pulsed Latches
t pd  Tc  max  t pdq , t pcq  tsetup  t pw  p p

          D1 Q1
Combinational Logic
D2 Q2

L1

L2
sequencing overhead
Tc
The two cases are if Tpw >
D1 tpdq
Tsetup (measured from
falling edge), or Tpw < (a) tpw > tsetup
Q1 tpd

Tsetup D2

The last case of Tpw < Tsetup p

means that the input arrives tpcq Tc tpw
before the rising edge to Q1 tpd tsetup

satisfy setup which is Tsetup- (b) tpw < tsetup

D2
Tpw, and add this to TCQ
when propagates through
logic

10: Sequential Circuits CMOS VLSI Design Slide 39

 Min-Delay: Flip-Flops
clk

tcd  Q1
CL

F1
clk

D2

F2
clk

Q1 tccq tcd

D2 thold

10: Sequential Circuits CMOS VLSI Design Slide 40

 Min-Delay: Flip-Flops
clk

tcd  thold  tccq Q1

CL

F1
clk

D2

F2
clk

Q1 tccq tcd

D2 thold

10: Sequential Circuits CMOS VLSI Design Slide 41

Min-Delay: 2-Phase Latches
1

tcd 1,tcd 2  Q1
CL

L1
2
Hold time reduced by D2

L2
nonoverlap
tnonoverlap
1
Paradox: hold applies tccq
twice each cycle, vs. 2

only once for flops. Q1 tcd

D2 thold

But a flop is made of

two latches!

10: Sequential Circuits CMOS VLSI Design Slide 42

Min-Delay: 2-Phase Latches
1

tcd 1,tcd 2  thold  tccq  tnonoverlap Q1

CL

L1
2
Hold time reduced by D2

L2
nonoverlap
tnonoverlap
1
Paradox: hold applies tccq
twice each cycle, vs. 2

only once for flops. Q1 tcd

D2 thold

But a flop is made of

two latches!

10: Sequential Circuits CMOS VLSI Design Slide 43

 Min-Delay: Pulsed Latches
p

tcd  Q1
CL

L1
p
Hold time increased
D2
by pulse width

L2
p
tpw
thold

Q1 tccq tcd

D2

10: Sequential Circuits CMOS VLSI Design Slide 44

 Min-Delay: Pulsed Latches
p

tcd  thold  tccq  t pw Q1

CL

L1
p
Hold time increased
D2
by pulse width, so

L2
desirable to keep p
tpw
pulse width short thold

Q1 tccq tcd

D2
Equation easier to understand as:
Tcd + Tccq >= Tpw+Thold
(because Thold occurs after falling edge)

10: Sequential Circuits CMOS VLSI Design Slide 45

 Time Borrowing
 In a flop-based system:
– Data launches on one rising edge
– Must setup before next rising edge
– If it arrives late, system fails
– If it arrives early, time is wasted
– Flops have hard edges
 In a latch-based system
– Data can pass through latch while transparent
– Long cycle of logic can borrow time into next
– As long as each loop completes in one cycle

10: Sequential Circuits CMOS VLSI Design Slide 46

Time Borrowing Example
1

2
1 2 1

Latch

Latch
Latch

Combinational
(a) Combinational Logic
Logic

Borrowing time across Borrowing time across

half-cycle boundary pipeline stage boundary
1 2

Latch
Latch

Combinational
(b) Combinational Logic Logic

Loops may borrow time internally but must complete within the cycle

10: Sequential Circuits CMOS VLSI Design Slide 47

 How Much Borrowing?
2-Phase Latches 1 2

T D1 Q1 D2 Q2
 c   tsetup  tnonoverlap 
Combinational Logic 1

L2
L1
tborrow
2
1

Pulsed Latches 2 tnonoverlap

Tc

tsetup
tborrow  t pw  tsetup Tc/2
Nominal Half-Cycle 1 Delay
tborrow

D2

10: Sequential Circuits CMOS VLSI Design Slide 48

 Clock Skew
 We have assumed zero clock skew
 Clocks really have uncertainty in arrival time
– Decreases maximum propagation delay
– Increases minimum contamination delay
– Decreases time borrowing

10: Sequential Circuits CMOS VLSI Design Slide 49

 Skew: Flip-Flops
clk clk

t pd  Tc   t pcq  tsetup  tskew 

Q1 D2
Combinational Logic

F1

F2
       Tc

sequencing overhead
clk

tcd  thold  tccq  tskew

tpcq
tskew

Q1 tpdq tsetup

D2

clk

Q1
CL

F1
clk

D2

F2
tskew

clk
thold

Q1 tccq

D2 tcd

10: Sequential Circuits CMOS VLSI Design Slide 50

 Skew: Latches
2-Phase Latches 1 2 1

2t  
D1 Q1 Combinational D2 Q2 Combinational D3 Q3

L1

L2

L3
t pd  Tc  pdq
Logic 1 Logic 2

sequencing overhead 1

tcd 1 , tcd 2  thold  tccq  tnonoverlap  tskew 2

Tc
tborrow    tsetup  tnonoverlap  tskew 
2
Pulsed Latches
t pd  Tc  max  t pdq , t pcq  tsetup  t pw  tskew 
            
sequencing overhead

tcd  thold  t pw  tccq  tskew

tborrow  t pw   tsetup  tskew 

10: Sequential Circuits CMOS VLSI Design Slide 51

 Two-Phase Clocking
 If setup times are violated, reduce clock speed
 If hold times are violated, chip fails at any speed
 In this class, working chips are most important
– No tools to analyze clock skew
 An easy way to guarantee hold times is to use 2-
phase latches with big nonoverlap times
 Call these clocks 1, 2 (ph1, ph2)

10: Sequential Circuits CMOS VLSI Design Slide 52

 Safe Flip-Flop
 In class, use flip-flop with nonoverlapping clocks
– Very slow – nonoverlap adds to setup time
– But no hold times
 In industry, use a better timing analyzer
– Add buffers to slow signals if hold time is at risk
  Q

X
D Q
 
 

 

10: Sequential Circuits CMOS VLSI Design Slide 53

 Summary
 Flip-Flops:
– Very easy to use, supported by all tools
 2-Phase Transparent Latches:
– Lots of skew tolerance and time borrowing
 Pulsed Latches:
– Fast, some skew tol & borrow, hold time risk

10: Sequential Circuits CMOS VLSI Design Slide 54