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NOW, WE WILL CONTINUE TO MAJOR PROJECT
8-BIT RISC MICROPROCESSOR USING VERILOG

BY
ASHISH TOMAR
UNDER SUPERVSION
ARPAN SHAH

JAGANNATH UNIVERSITY
 What is RISC ?

RISC = Ridiculously Simple Computer

Or

RISC = Reduced Instruction Set Computers

1) Small Instruction Set

2) Load/Store Architecture

3) Fixed Length Coding And Hardware Decoding

4) Large Register Set

5) delayed branching

6) processor throughput of one instruction per cycle in average

RISC processor will cost less to design -- since a significant
cost of the chip can be the actual R&D costs to create it,
this can be substantial on its own

easier to design (and fewer bugs) means that the processor

will have a faster time to market

faster time to market means the processor can use newer

processes

simpler to design means that they have more time for adding
other things (things that can make the processor do more in
each cycle)

more design time also means that you can tune the processor
more to get more MHz (more cycles) and many other
effects
What’s an FPGA?
FPGA – FIELD PROGRAMMABLE GATE ARRAY
 Field Programmable Gate Arrays
FPGA

Field Programmable Gate Array

New Architecture
‘Simple’ Programmable Logic Blocks
Massive Fabric Of Programmable Interconnects

Large Number Of Logic Block ‘Islands’

1,000 … 100,000+
In A ‘Sea’ Of Interconnects
 Logic

Standard
ASIC
Logic

Programmable Gate Cell-Based Full custom

Logic Devices Arrays ICs ICs

SPLDs CPLDs FPGAs FPICs

1.Create a circuit design
1.1-Graphic circuit tool
1.2-Verilog
1.3-VHDL
1.4-AHDL
2.Compile the design for the selected device
3.Download the compiled configuration
Hardware Description Languages(HDL)
1.Basic idea is a programming language to
describe hardware
2.Initial purpose was to allow abstract design
and simulation
3.Design could be verified then implemented in
hardware
4.Now Synthesis tools allow direct
implementation from HDL code.
4.1.Large improvement in designer
productivity
1.Combined with modern Field Programmable Gate Array chips large
complex circuits (100000s of gates) can be implemented.
2.There are many different HDLs
2.1-Verilog HDL
2.2-ABEL
2.3-VHDL
3.VHDL is the most common
3.1-Large standard developed by US DoD
3.2-VHDL = VHSIC HDL
3.3-VHSIC = Very High Speed Integrated Circuit
Verilog HDL
 Verilog HDL is second most common
 Easier to use in many ways = better for teaching
 C - like syntax
 History
 Developed as proprietry language in 1985
 Opened as public domain spec in 1990
 Due to losing market share to VHDL
 Became IEEE standard in 1995
Verilog HDL
 Verilog constructs are use defined keywords
 Examples: and, or, wire, input output
 One important construct is the module
 Modules have inputs and outputs
 Modules can be built up of Verilog primatives or of user
defined submodules.
Example: Simple Circuit Diagram

All examples and code from Mano “Digital Design” 3rd Ed.
Example: Simple Circuit HDL
module smpl_circuit(A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and g1(e,A,B);
not g2(y, C);
or g3(x,e,y);
endmodule
FUNCTIONAL DESCRIPTION
OF 8 BIT RISC PROCESSOR

Functional Block Diagram

TOL LEVEL ENTITY
RISC PROCESSOR CONSIST OF
MOVE UNIT
SHIFT UNIT
ARTHMETHIC UNIT
PROGRAM COUNTER
INSTRUCTION REGISTER
INSTRUTION DECODER
CONTROL UNIT
DATA MEMORY
PROGRAM MEMORY
The move unit performs two instructions:
---MOV dst, src
---MVI, immediate data
RISC - SHIFT UNIT
The shift unit performs two instructions:
SL dst, src
SR dst, src
RISC - ARTHMETHIC UNIT
The arithmetic unit performs five instructions:
1. INC dst, src
2. DEC dst, src
3. ADD src
4. SUB src
5. CMP src

src A Cin Sub I[8] q_S q_C

8 8

ARITHMETIC UNIT

Result_au S C Z
FUNCTIONALITY OF ARITHMETHIC UNIT
1. INC: The 2nd input to the adder is 0 and Cin is high, so the result comes out
to be source +1
2. DEC: The 2nd input is Zero, Sub is high and Cin is low, the result is source +
1’s complement of 0 i.e. 1111_1111 which is also the 2’s complement of 1. So
the result comes out to be source – 1
3. ADD: Cin and Sub both are low, so the 2nd input i.e. A, is passed as it is. The
result comes out to be source + contents of register A.
4. SUB: Cin and Sub both are high, so the 2nd input i.e. A, is converted to its 2’s
complement form i.e. its negative value. The result comes out to be source -
contents of register A.
5.CMP: Its functionality is exactly the same as Sub, the only difference being
that the result in this case is not stored in any register.
This unit performs three instructions:
q14
1. JMP immediate offset
16
2. JZ immediate offset CD

3. JMPCD 16

rst PROGRAM S4
COUNTER 0
clk
I[9:2]
8
8 0000-
16 16-BIT ADDER 0001

Address Lines for

Program Memory
 INSTRUCTION REGISTER
The instruction register is a 11-bit triggered register. It loads the
instructions on the positive edge of the clock. The instruction to the
instruction register is fed from the program memory. The address for
the program memory is taken by the value of the program counter.

INSTRUCTION DECODER
This unit is used to identity the instruction being executed. The
input to this unit is the op-code part of the instruction which comes
from the instruction register. Output of this unit is a 14-bit port
where each bit represents one of the 14 instructions. All the
instructions have different operation codes, so at time only one of
the 14 bits will be high in the output
RISC – CONTROL UNIT
Control unit generates many control
signals required by different
modules and the top level entity.
The inputs to the control unit are
Decoded Instructions from the
instruction decoder and the values
of the flags. The output is many
control signals.
RISC – DATA AND PROGRAM
MEMORY
DATA MEMORY
The data memory is a block RAM of size 65kbytes. The data memory
has a synchronous write and asynchronous read. The address lines for it
comes from the concatenation of the contents of the registers C & D.
The data line for the memory is bidirectional. Write and Read
operations are controlled by the wr_data and rd_data signals generated
by the control unit.

PROGRAM MEMORY
The program memory is a block RAM with 65536 locations and 11 bits
per location. This stores the instructions to be executed by the processor.
Read operation is asynchronous. The address line for the program
memory comes from the 16-bit program counter.
 Summary
Programmable Logic Devices
Basics
Evolution

Field Programmable Gate Arrays (FPGAs)

Architecture

Design Flow
Hardware Description Languages
Design Tools

Trends

Importance for Particle Physics Experiments

[1] R. Aceves, Desarrollo de un enlace inalámbrico para
telefonía fija empleando una FPGA. Final Project at the
ETSII, University of Valladolid, Spain, 2006.

[2] M. Alonso, Diseño de un Entorno de Desarrollo de Alto

y Bajo Nivel para un Procesador de Propósito General
integrado en FPGA, Final Project at the ETSII,
University of Valladolid, Spain, 2003.

[3] J. del Barrio, Desarrollo sobre FPGA de un Emulador de

una Planta de Microgeneración Eléctrica, Final Project
at the ETSII, University of Valladolid, Spain, 2004.

[4] K. Chapman, “PicoBlaze 8-Bit Microcontroller for

Virtex-E and Spartan-II/IIE Devices”, Xilinx XAPP213
(v2.0), online at http://www.xilinx.com/xapp/xapp213
.pdf, December, 2002
THANK YOU