ECOM 4311

Digital System Design using VHDL

Chapter 10

Finite State Machines

F INITE STATE MACHINES

• (FSM) is a digital system whose outputs

are a function of both its present input
values and its past history of input values.
• Information characterizing the effect of a
FSM’s past history of input values is
provided by its state (present state ).
• Physically, a FSM’s state is represented by
the value stored in a register called the
state register.

2
Logic Diagram

3
Fully Synchronous FSM

4
Present State
• The present state is stored as a binary
value in the state register.
• The number of memory elements in the
state register is finite. If the state register
has n memory elements, the maximum
number of unique states the FSM can have
is 2n. This number is also finite, hence the
name finite state machine.

5
Next State
• The combinational logic also computes the
next state value from the FSM’s inputs and
present state. This value is provided to the
inputs of the state register.
• At each triggering clock edge, the next
state value is clocked into the state register
and becomes the new present state value.

6
Outputs

• A FSM’s outputs are computed by

combinational logic that receives two sets
of inputs. One set is the external inputs to
the FSM. The other set is the FSM’s
present state.
• FSMs can be classified as either Mealy or
Moore. These two kinds of FSMs differ in
how their outputs are computed.

7
8
Mealy FSMs
• Mealy FSM’s outputs are a function of both
its inputs and its present state. Because of
this, the outputs of a Mealy FSM can
change as soon as any of its inputs
change.
• However, its state still cannot change until
a triggering clock edge.

9
Moore FSMs
• A Moore FSM’s outputs are a function of only its
present state.
• since a Moore FSM’s outputs are a function of only
its present state, they can change only at a
triggering clock edge.
• In general, any sequential function can be
implemented by either a Mealy FSM or a Moore
FSM.
• However, while a Moore FSM is often conceptually
simpler, it usually requires more states than a
Mealy FSM to implement the same function.
• A FSM does not have to be exclusively Mealy or
Moore. It can be a combination of both, having
some outputs (Mealy outputs) and other outputs
(Moore outputs).
10
11
FSM STATE DIAGRAMS
• A state diagram provides an abstract graphical
representation of the operation of FSM.
• It allows the conceptualization of the FSM’s
operation to be separated from its
implementation.
• Each individual state of the FSM is
represented by a state circle, with the state’s
name or its encoding located inside.
• Directed arcs show the possible transitions
from one state to another and under what
input conditions each transition will occur.
12
FSM STATE DIAGRAMS
A state diagram must have a reset state

13
FSM STATE DIAGRAMS

• For a state diagram to be completely

specified, for every state the output and
next state transition must be shown for all
possible input combinations.
• In some FSMs a transition from one
particular state to another may be
unconditional. The directed arc for such a
transition will not be labeled with an input
value.

14
State Table

The same information presented in a state diagram can

be presented in a state table
15
THREE-PROCESS FSM VHDL TEMPLATE

• Once a FSM’s state diagram has been

created, its VHDL code can be written. There
are many ways a FSM can be described in
VHDL.
• One straightforward way is to code each block
in Figure 10.1.2 as a separate process. The
result is a description consisting of three
processes:
o One describes the state register.
o The other two describe the output combinational
logic and the next state combinational logic.
16
17
18
19
Two- and One- Process FSM Templates

• The three-process FSM template has the

advantage that it is a one-to-one
conceptual mapping to the FSM block
diagram in Figure 10.1.2.
• It also has the advantage, from the coding
perspective, that it is very readable and
easy to modify and maintain.
• However, it is certainly not the only
template that we can use for an FSM.

20
Two- Process FSM Templates

• One common variation is to use two

processes and a set of conditional signal
assignment statements.
• In this approach, the state register and
next state logic are implemented using
processes as before.
• The output logic is implemented by the set
of conditional signal assignment statements
using one statement for each output.
.
21
One- Process FSM Templates

• Another FSM template variation uses one

process to describe both the state register
and next state logic, and uses conditional
signal assignment statements for the output
logic.
• Regardless of the approach used, if the
same FSM is described, the resulting
synthesized logic is the same.

22
Positive Edge Detector State Diagram

23
Positive Edge Detector State Diagram

• The purpose of the positive edge detector

is to detect a 0 to 1 transition on input a.
There are two conditions that must be met
to detect a 0 to 1 transition on a.
o First, a must be 0 at a triggering clock edge.
o Second, a must be 1 at the next triggering
clock edge.

24
Positive Edge Detector State Diagram

• First we need a state for the FSM to be placed

in when it is reset by asserting clr_bar. This
state was abstractly named state_a.
• in state_a, if a is 1 at the next triggering clock
edge, nothing of interest has occurred and the
FSM transitions back to state_a.
• However, if a is 0 at the next triggering clock
edge, we have met the first condition. The
FSM must denote this event by transitioning to
a new state. We can name this state state_b.
25
Positive Edge Detector State Diagram

• In state_b, if a is 0 at the next triggering

clock edge, nothing of significance has
occurred while in this state, so the
transition is back to state_b.
• However, if a is a 1 at the next triggering
clock edge, the FSM has detected a
positive edge.
• This event is denoted by transitioning to a
new state, state_c. In state_c, output a_pe
is 1.
26
Positive Edge Detector State Diagram

• Since the output is to be 1 for only one clock

period after a positive edge on a has been
detected, we must transition out of state_c at
the next triggering clock edge, regardless of
the value of a.
• If a is 0 at the next triggering clock edge, we
have met the first condition for a new positive
edge on a, so the transition is to state_b.
• If instead, a is 1 at the next triggering clock
edge, we must wait for it to become 0 before
we can detect the next positive edge, so the
transition is to state_a.
27
Positive Edge Detector VHDL description

• From the state diagram, a description of the edge detector

can be written. This description, which follows the
template in Listing 10.3.1, is given in Listing 10.4.1.

28
29
30
31
32
Mealy FSM Edge Detector

33
34
35
36
37
COUNTERS AS MOORE FSMS

• A simple counter is a
special case of a
Moore FSM where
there are no inputs
(other than the clock
and reset) and the
outputs are taken
directly from the state
register.

38
2-bit Binary Counter FSM

39
Counter with state encoding defined by
constants

40
41
42
Finally….

?
Any Questions

43