Professional Documents
Culture Documents
• OEM: HUAWEI
1 1 / 7 / 2 0 1 8 2 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
Engineering
Toolbox
• 3900 series
• BBU+RFU
• BBU+RRU
– Distributed Base Station
• BBU+AAU
1 1 / 7 / 2 0 1 8 4 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
3900 series
1 1 / 7 / 2 0 1 8 5 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
1 1 / 7 / 2 0 1 8 6 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
HERT platform
1 1 / 7 / 2 0 1 8 8 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
NodeB block diagram
1 1 / 7 / 2 0 1 8 9 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
eNodeB block diagram
1 1 / 7 / 2 0 1 8 10 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
BBU3900
Access Tech Type Card combination: required + (optional)
GSM GBTS GTMU + (UTRP)
WCDMA NodeB WMPT/UMPT + WBBP + (UTRP)
LTE eNodeB LMPT/UMPT + LBBP + (UTRP)
GU, GL, UL, GUL MBTS 2~3 BTS’s with multimode RXUs
Card Function Full Name
GTMU Ctrl GSM Transmission and Timing and Management Unit
WMPT Ctrl WCDMA main processing and transmission unit
LMPT Ctrl LTE main processing and transmission unit
UMPT Ctrl Universal main processing and transmission unit
UTRP Transport Universal transmission processing unit
WBBP BB WCDMA baseband processing unit
1 1 / 7 / 2 0 1 8 11 w w w . i q o r . c o m
© 2 0 1 5 , LBBP
i Q o r . A l l r i g h t s BB
r e s e r v e d LTE baseband processing unit .
RRUs
1 1 / 7 / 2 0 1 8 12 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
DBS3900 Plano Lab Setup
• BBU3900 WCDMA NodeB • RRU 3936 1800 Band
WBBPb4 WCDMA BaseBand Processing Unit (WBBP) falls into the following types:
l WBBPa
l WBBPb
l WBBPd
l WBBPf
UMTS only
1 1 / 7 / 2 0 1 8 13 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
RRU 3936 ports
1 1 / 7 / 2 0 1 8 14 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
RRU3936 spec
1 1 / 7 / 2 0 1 8 15 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
RRU3936 Block Diagram
1 1 / 7 / 2 0 1 8 16 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
RRU3936 internal structure
1 1 / 7 / 2 0 1 8 17 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
RRU3936 internal structure
1 1 / 7 / 2 0 1 8 18 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
RF Board to Board jumper
• 4x Special board to board jumper used in RRU3936
– Jumper has SMP Female on RF board end.
– UNKNOWN type on PA end.
• USE SMP Male to Male with the original jumper to interface
with PA board, enabling PA modular test.
1 1 / 7 / 2 0 1 8 19 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
RF Board to Board jumper
1 1 / 7 / 2 0 1 8 20 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
Testing Methods
• System test + Unit test + Module test (PA, filter, Power Supply)
– System required: No available RRU built-in test
• Percentage of coverage
– With system 75%
– Unit 40% (boot process monitoring)
– PA, Filter, Power Supply 100%
• Projected parts more likely to fail
– PA (Amplifier FETs)
– Power Supply (caps, MOSFET, fuses, regulators, etc)
1 1 / 7 / 2 0 1 8 21 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
System Test
• Commissioning BBU3900
– LMT
– Configuration file Editing
– Adding RRU
• RRU related test
– VSWR test
– Heath Check
– Manufacturer information
– CPRI BER Test
1 1 / 7 / 2 0 1 8 22 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
Commissioning BBU3900
• In lab environment, commission is done through Huawei LMT
(Local Management Terminal) software .
– Configuration is normally created with iManager U2000 MBB
(we don’t have), and can be downloaded to BTS using LMT.
– Alternatively, configuration is grabbed (uploaded) from a
random BTS3900, altered and re-downloaded, all with LMT.
1 1 / 7 / 2 0 1 8 23 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
LMT
• MML Commands
• Maintenance tasks
– Data Configuration File transfer
– SW update
1 1 / 7 / 2 0 1 8 24 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
BTS structure
• NodeB • Site
– Cabinet – Sector
• Sub-rack • Local Cell
– Slot
» Card
» RRU Chain
• RRU position
• RRU
» RFU
1 1 / 7 / 2 0 1 8 25 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
MML Commands
1 1 / 7 / 2 0 1 8 26 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
Data Configuration File transfer
1 1 / 7 / 2 0 1 8 27 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
Editing Configuration File
<Cabinet id="2"> 137 BTS3900L
<attributes>
• XML file <CN>0</CN>
135 (FAIL) RFC
<TYPE>137</TYPE> 138 BTS3900AL
• Cabinet type <= 143 <DESC></DESC>
143 BTS3900D
</attributes>
• NE type <= 14 </Cabinet> 154 tp48600A
1 1 / 7 / 2 0 1 8 28 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
Add RRU to empty DBS
• Add Cabinet (BTS3900D)
• Add Subrack (0 for boards, 60 for RRU)
• Add Board (WBBP WMPT FAN UPEU )
• Add RRU (MRRU to subrack 60, chain 0 trunk, position 0)
Display Board
-------------
Cabinet No. Subrack No. Slot No. Config Type SubBoard Type Administrative state StandBy Status Operational State Alarm Status Availability Status
1 1 / 7 / 2 0 1 8 29 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
RRU Manufacturing information
1 1 / 7 / 2 0 1 8 30 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
Alive Test: RRU Health Check
1 1 / 7 / 2 0 1 8 31 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
CPRI BER test
1 1 / 7 / 2 0 1 8 33 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
TX and FB test: VSWR Test
1 1 / 7 / 2 0 1 8 34 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
Unit test
• Health check without disassembling
– Boot process monitoring through serial interface
– LED status
1 1 / 7 / 2 0 1 8 35 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
RS232 serial interface
RS232 port EXT_ALM Pin
IN P9
OUT P8
GND P7
1 1 / 7 / 2 0 1 8 36 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
Boot process monitoring
• VxWorks RTOS
• Very limited commands available, more research needed.
• Serial interfaced disabled once RRU connected to BBU.
C0->BootTovxWorks
0.Boot to <BIN/MRRU.BIN> now......
Load Product VxWorks Image now....
0x5a390f8 (tShell0): tool: inflate, unzipped 18791984 bytes, used 2 seconds
BSP_LoadProductVxworks: unzip complete!
]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]
]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]
]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]
]]]]]]]]]]] ]]]] ]]]]]]]]]] ]] ]]]] (R)
] ]]]]]]]]] ]]]]]] ]]]]]]]] ]] ]]]]
]] ]]]]]]] ]]]]]]]] ]]]]]] ] ]] ]]]]
]]] ]]]]] ] ]]] ] ]]]] ]]] ]]]]]]]]] ]]]] ]] ]]]] ]] ]]]]]
]]]] ]]] ]] ] ]]] ]] ]]]]] ]]]]]] ]] ]]]]]]] ]]]] ]] ]]]]
]]]]] ] ]]]] ]]]]] ]]]]]]]] ]]]] ]] ]]]] ]]]]]]] ]]]]
]]]]]] ]]]]] ]]]]]] ] ]]]]] ]]]] ]] ]]]] ]]]]]]]] ]]]]
]]]]]]] ]]]]] ] ]]]]]] ] ]]] ]]]] ]] ]]]] ]]]] ]]]] ]]]]
]]]]]]]] ]]]]] ]]] ]]]]]]] ] ]]]]]]] ]]]] ]]]] ]]]] ]]]]]
]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]
]]]]]]]]]]]]]]]]]]]]]]]]]]]]] Development System
]]]]]]]]]]]]]]]]]]]]]]]]]]]]
]]]]]]]]]]]]]]]]]]]]]]]]]]] VxWorks 6.8
1 1 / 7 / 2 0 1 8 ]]]]]]]]]]]]]]]]]]]]]]]]]] KERNEL: WIND version 2.13 37 w w w . i q o r . c o m
]]]]]]]]]]]]]]]]]]]]]]]]] Copyright Wind River Systems, Inc., 1984-2009
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
LED status
• Normal:
– RUN Flashing Green
– ACT Flashing Green
– CPRI0 or 1 Solid Green
• ALM flashing: Configuration Failure
• ALM solid: Hardware Failure
1 1 / 7 / 2 0 1 8 38 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
Module tests
• TX path: PA + Filter + duplexer
• RX path: Filter + duplexer
• DC Power rails
1 1 / 7 / 2 0 1 8 39 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
Module level test: TX path
• Associated equipment
– Network analyzer
– DC power supply (30V 20A minimum)
– Coupler (40 or 50 dB), terminator (check power rating).
– Cables, Adapters.
– Aardvark I2C/SPI Host Adapter (Or equivalent)
– Vector Signal Analyzer
– Vector Signal Generator
1 1 / 7 / 2 0 1 8 40 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
Amplifier Structure
1 1 / 7 / 2 0 1 8 41 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
1 1 / 7 / 2 0 1 8 42 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
Module level test: PA Components
1 1 / 7 / 2 0 1 8 43 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
Bias voltages
When running
VSWR test.
(AMP ON)
1 1 / 7 / 2 0 1 8 44 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
PA interface reverse engineering
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
27.9V 27.9V 27.9V GND GND GND GND FB_S GND FB_S GND GND ALDA GND GND ALDB NC NC NC
W1 W2
3V 0V
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
27.9V 27.9V 27.9V GND GND GND 2.87V GND 5.39V GND SDI GND SCLK GND CS_n SDO GND NC NC NC
AMP VDD
EN
1 1 / 7 / 2 0 1 8 45 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
PA interface reverse engineering
• Sniff SPI interface during
VSWR test:
• INIT sequence
• IDLE measurements
• AMP ON sequence
• AMP OFF sequence
• Register operations on
AMC7812 controller
• WARNING: DO NOT USE
REGULAR RIBBON CABLE.
This 40pin cable has to be
a “crossover”.
1 1 / 7 / 2 0 1 8 46 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
40pin “crossover” ribbon cable
• Pin 1 to Pin2
• Pin 2 to Pin1
• Pin 3 to Pin4
• Pin 4 to Pin3
• And so on…
• Measure and Make sure
1 1 / 7 / 2 0 1 8 47 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
SPI command sequences
• INIT: set controller operation mode, zero all DACs.
NT W W ADD WD R ADD Register name
W7C 7C 66 00 Software Reset <spi_write io="0" count="3" radix="16"> 7C 66 00 </spi_write> <sleep ms="1"/>
W4C 4C 24 00 AMC Configuration 0 <spi_write io="0" count="3" radix="16"> 4C 24 00 </spi_write> <sleep ms="1"/>
W4D 4D 00 70 AMC Configuration 1 <spi_write io="0" count="3" radix="16"> 4D 00 70 </spi_write> <sleep ms="1"/>
W4E 4E 00 00 Alarm Control <spi_write io="0" count="3" radix="16"> 4E 00 00 </spi_write> <sleep ms="1"/>
W50 50 7F FF ADC Channel 0 <spi_write io="0" count="3" radix="16"> 50 7F FF </spi_write> <sleep ms="1"/>
W51 51 70 00 ADC Channel 1 <spi_write io="0" count="3" radix="16"> 51 70 00 </spi_write> <sleep ms="1"/>
W52 52 FF FF ADC Gain <spi_write io="0" count="3" radix="16"> 52 FF FF </spi_write> <sleep ms="1"/>
W0A 0A 00 0C Temperature Configuration <spi_write io="0" count="3" radix="16"> 0A 00 0C </spi_write> <sleep ms="1"/>
W0B 0B 00 07 Temperature Conversion Rate <spi_write io="0" count="3" radix="16"> 0B 00 07 </spi_write> <sleep ms="1"/>
W58 58 00 00 DAC Configuration <spi_write io="0" count="3" radix="16"> 58 00 00 </spi_write> <sleep ms="1"/>
W59 59 00 00 DAC Gain <spi_write io="0" count="3" radix="16"> 59 00 00 </spi_write> <sleep ms="1"/>
W6B 6B 7F FE Power-Down <spi_write io="0" count="3" radix="16"> 6B 7F FE </spi_write> <sleep ms="1"/>
W4C 4C 34 00 AMC Configuration 0 <spi_write io="0" count="3" radix="16"> 4C 34 00 </spi_write> <sleep ms="1"/>
W33 33 00 00 DAC-0-Data <spi_write io="0" count="3" radix="16"> 33 00 00 </spi_write> <sleep ms="1"/>
W35 35 00 00 DAC-2-Data <spi_write io="0" count="3" radix="16"> 35 00 00 </spi_write> <sleep ms="1"/>
W36 36 00 00 DAC-3-Data <spi_write io="0" count="3" radix="16"> 36 00 00 </spi_write> <sleep ms="1"/>
W38 38 00 00 DAC-5-Data <spi_write io="0" count="3" radix="16"> 38 00 00 </spi_write> <sleep ms="1"/>
W39 39 00 00 DAC-6-Data <spi_write io="0" count="3" radix="16"> 39 00 00 </spi_write> <sleep ms="1"/>
W3A 3A 00 00 DAC-7-Data <spi_write io="0" count="3" radix="16"> 3A 00 00 </spi_write> <sleep ms="1"/>
W3B 3B 00 00 DAC-8-Data <spi_write io="0" count="3" radix="16"> 3B 00 00 </spi_write> <sleep ms="1"/>
1 1 / 7 / 2 0 1 8 48 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
SPI command sequences
• AMP ON: set DAC 0,2,3,5,6,7 and 8 to desired output level.
NT W W ADD WD R ADD Register name
W33 33 00 00 DAC-0-Data <spi_write io="0" count="3" radix="16"> 33 00 00 </spi_write> <sleep ms="1"/>
W35 35 00 00 DAC-2-Data <spi_write io="0" count="3" radix="16"> 35 00 00 </spi_write> <sleep ms="1"/>
W36 36 00 00 DAC-3-Data <spi_write io="0" count="3" radix="16"> 36 00 00 </spi_write> <sleep ms="1"/>
W38 38 00 00 DAC-5-Data <spi_write io="0" count="3" radix="16"> 38 00 00 </spi_write> <sleep ms="1"/>
W39 39 00 00 DAC-6-Data <spi_write io="0" count="3" radix="16"> 39 00 00 </spi_write> <sleep ms="1"/>
W3A 3A 00 00 DAC-7-Data <spi_write io="0" count="3" radix="16"> 3A 00 00 </spi_write> <sleep ms="1"/>
W3B 3B 00 00 DAC-8-Data <spi_write io="0" count="3" radix="16"> 3B 00 00 </spi_write> <sleep ms="1"/>
W3B 3B 09 C3 DAC-8-Data <spi_write io="0" count="3" radix="16"> 3B 09 C3 </spi_write> <sleep ms="1"/>
W3A 3A 04 27 DAC-7-Data <spi_write io="0" count="3" radix="16"> 3A 04 27 </spi_write> <sleep ms="1"/>
W39 39 04 27 DAC-6-Data <spi_write io="0" count="3" radix="16"> 39 04 27 </spi_write> <sleep ms="1"/>
W38 38 09 CA DAC-5-Data <spi_write io="0" count="3" radix="16"> 38 09 CA </spi_write> <sleep ms="1"/>
W36 36 0A 2E DAC-3-Data <spi_write io="0" count="3" radix="16"> 36 0A 2E </spi_write> <sleep ms="1"/>
W35 35 04 FA DAC-2-Data <spi_write io="0" count="3" radix="16"> 35 04 FA </spi_write> <sleep ms="1"/>
W33 33 0B 3A DAC-0-Data <spi_write io="0" count="3" radix="16"> 33 0B 3A </spi_write> <sleep ms="1"/>
NOTE: AMP will not turn on without 2.87V applied on pin 14.
1 1 / 7 / 2 0 1 8 49 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
SPI command sequences
• AMP OFF: zero DACs.
NT W W ADD WD R ADD Register name
W33 33 00 00 DAC-0-Data <spi_write io="0" count="3" radix="16"> 33 00 00 </spi_write> <sleep ms="1"/>
W35 35 00 00 DAC-2-Data <spi_write io="0" count="3" radix="16"> 35 00 00 </spi_write> <sleep ms="1"/>
W36 36 00 00 DAC-3-Data <spi_write io="0" count="3" radix="16"> 36 00 00 </spi_write> <sleep ms="1"/>
W38 38 00 00 DAC-5-Data <spi_write io="0" count="3" radix="16"> 38 00 00 </spi_write> <sleep ms="1"/>
W39 39 00 00 DAC-6-Data <spi_write io="0" count="3" radix="16"> 39 00 00 </spi_write> <sleep ms="1"/>
W3A 3A 00 00 DAC-7-Data <spi_write io="0" count="3" radix="16"> 3A 00 00 </spi_write> <sleep ms="1"/>
W3B 3B 00 00 DAC-8-Data <spi_write io="0" count="3" radix="16"> 3B 00 00 </spi_write> <sleep ms="1"/>
1 1 / 7 / 2 0 1 8 50 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
“Driving the Power AMP”
1 1 / 7 / 2 0 1 8 51 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
“Driving the Power AMP”
TX:1805~1880MHz
1 1 / 7 / 2 0 1 8 53 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
TX path (AMP) P-out vs P-in
1 1 / 7 / 2 0 1 8 54 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
Module test: RX path (passive)
• Associated equipment
– Network analyzer
– Cables, Adapters.
1 1 / 7 / 2 0 1 8 55 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
RX2 path S21
TX:1805~1880MHz
RX:1710~1785MHz
1 1 / 7 / 2 0 1 8 56 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
RX1 path S21
TX:1805~1880MHz
RX:1710~1785MHz
1 1 / 7 / 2 0 1 8 57 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
Module test: DC-DC rails
• Measure at DC voltage probe points
• Makes sure all voltages are present and within tolerance.
• List of DC probe points provided as a separate document.
1 1 / 7 / 2 0 1 8 58 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
Future work
• Is it possible to test the RRU through command line interface?
• “JTAG” port investigation
1 1 / 7 / 2 0 1 8 59 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
General Notes
• Possible issues
– Mechanical
• Slow disassembly: special screw, thermal pads under PCB
– Electronic
• Digital problems will be time-consuming to troubleshoot
• RF FETs will be expensive, some hard to source.
• FETs bias may need to be adjusted after replacement
• Hi-Silicon (Huawei IC) chips will be very hard to source
• Skill set required
– RF Fundamentals
– RF and digital circuit debug and repair experiences
1 1 / 7 / 2 0 1 8 60 w w w . i q o r . c o m
© 2 0 1 5 , i Q o r . A l l r i g h t s r e s e r v e d .
Thank you! Q & A
7 / 5 / 2 0 1 6