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Chiu
EECT 7327 Fall 2014
–1–
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
V(t)
• T/2 acquisition time
• Finite bandwidth
H T H T H T H T H T
• Practical
0 T 2T t
T/2
–2–
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
CMOS
W
1
Ron μCox VDD Vth Vi 0 Vi VDD
L
–3–
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
RS Ron Ron
Vi CS Vo
–4–
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
Dispersion
|H(jω)|
1 • Magnitude response
• Non-uniform phase delay
• Non-uniform group delay
0 ω0 ω
Phase delay :
H(jω)
ω0 ω H jω
0 t p ω
ω
-45° Group delay :
-90° t g ω
d
H jω
dω
–5–
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
Dispersion
RS Ron
Vi CS Vo
t t
–6–
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
Signal-Dependent Ron
Ф
RS Ron
Vo PMOS
NMOS
Vi CS VTp VTn
CMOS
W
1
Ron μCox VDD Vth Vi 0 Vi VDD
L
–7–
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
Ideal T/H
V(t)
–8–
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
δ2
δ1
Droop
Δt
Hold Track Hold t
–9–
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
Vi CS Vo 1% (7b) ≥ 5t
0.1% (10b) ≥ 7t
1
τ RS Ron CS 0.01% (13b) ≥ 9t
TBW
1 L2 L2
Ron
μCox
W
VDD Vth Vi μC ox WL VDD Vth Vi μQch
L
Short L, thin tox, large W, large Vov, and small Vi help reduce Ron
– 10 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
δ2
δ1
Droop
Δt
Hold Track Hold t
Switch Non-Idealities
Ф
VDD Vin+Vth
Zi Cgs Cgd
Vout Ф
0
Vin Qch CS
Switch on Switch off
– 12 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
Slow turn-off:
Vo 1 ε Vi Vos
Cgs Cgs
Vo 1 V
C C i C C th
V
gs S gs S
Fast turn-off:
Vo 1 ε Vi Vos
– 13 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
1 Q ch
Pedestal error: ΔV
2 CS
1 μQ
TBW: TBW 2 ch
RonCS L CS
ΔV 1 Qch L2CS L2
Therefore:
TBW 2 CS μQch 2μ
– 14 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
CH 1
Φ1
Vin Φ1
Φ2
CH 2
Φ2
– 15 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
Aperture Jitter
V(t)
dV
dt
δV
δt
Track Hold t
– 16 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
Aperture Jitter
Vi t Asin ω t δt
Asin ωt cos ωδt Acos ωt sin ωδt
ωδt ωδt ωδt
Asin ωt 1 sin2 Acos ωt 2sin cos
2 2 2
Asin ωt ωδt Acos ωt for small δt
T0 2 2
A2 A 2ω2σ t 2 1
SNR
2
2
2 2
ωσ
t
– 17 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
Aperture Jitter
140
= 0.1ps
t
120 = 1ps
t
= 10ps
t
= 100ps
100 t
SNR [dB]
80
60
40
20
SNR 20 LOG10 ωσt
0 6 7 8 9
10 10 10 10
Input Freq [Hz]
– 18 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
δ2
δ1
Droop
Δt
Hold Track Hold t
– 19 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
2
1 kT
VN 4kTR df
2
kT/C noise: 0 1 j2π f RC S CS
T = 300K
CS √kT/C
100pF 6.4μV
2
Vi
SNDR 1pF 64μV
SNDR: A 2ω 2 2
VN δt Vε
2 2
2 10fF 640μV
Noise Distortion
Jitter
– 20 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
– 21 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
Pros
• Simple, minimum number of devices
• Potentially wideband, zero track-mode offset
Cons
• Signal-dependent tracking bandwidth
• Signal-dependent charge injection and clock feedthrough
• Signal-dependent aperture delay (sampling point)
– 22 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
VDD
Vi+Vth(Vi)
Vi t Asin ωt
Ф V t
Vth(Vi) Vo t Asin ω t i
0 SR
Switch on Switch off
– 23 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
Signal Distortion
V
Vo t Asin ω t i
SR
V V
Asin ωt cos ω i Acos ωt sin ω i
SR SR
V V
Asin ωt ω i Acos ωt for small i
SR SR
V
ε t Vi t Vo t ω i Acosωt
SR
Asinωt ω 1 2
ε t ω Acosωt A sin2 ωt ← 2nd-order
SR SR 2
2
A 2ω
SDR
A2 2 SR 4 SR
2
2 2 A 2ω 2
– 24 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
CMOS Switch
Ron
Ф PMOS
NMOS
Vi Vo VTp VTn
CS
Ф CMOS
0 Vi VDD
– 25 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
Clock Bootstrapping
Ron
Φ Φ
VDD
In Out
M1
0 Vi VDD
– 26 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
Clock Bootstrapping
VDD
Φ
M5 M6 M2
M4 M3
C1 C2 C Φ
Φ
Φ Φ
Out
M1
Φ
Φ In
VSS
Ref: A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline ADC,”
IEEE Journal of Solid-State Circuits, vol. 34, issue 5, pp. 599-606, 1999.
– 27 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
Φ
Φ M2
M3
Φ
C Φ
Φ Φ
Out
M1
Φ
Φ In
VSS
– 28 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
Φ
Φ M2
M3
Φ
C Φ
Φ Φ
Out
M1
Φ
Φ In
VSS
– 29 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
Dummy Switch
Ф Ф
Vi Vo
W W
L CS 2L
– 30 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
Ф Ф
• TBW
Vi Vo
W W • Parasitics
CS L CS 2L
– 31 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
Fully-Differential T/H
Ф E.g.
– 32 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
Bottom-Plate Sampling
Ф
CS X
Vi
Фe Ф
Фe
Ф
– 33 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
Sample-and-Hold Amplifier
(SHA)
– 34 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
Inverting SHA
CH+
Ф1 Ф1 Ф1 Ф1e
CS+ Ф2
Vi+ Vo+
Ф2 Ф1e
Ф2
Vi- Vo-
CS- Ф2
Ф1 Ф1
T H
CH-
– 35 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
Ф1 Ф1
CS+
W
Vi+ L/2
W
Ф1e Ф1e Ф1e
L W
Vi- L/2
CS-
Ф1 Ф1
CH-
– 36 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
C S+ Ф2
Vo+
• CM?
Ф2
Vo- • DM?
C S- Ф2
CH-
– 37 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
Differential Mode
CH+
DM half circuit
Ф2
CS + Ф2 CH
Vo+
Ф2
Vo-
CS
Vo+
Ф2
C S- Ф2 Vi,dm Adm
CH-
– 38 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
Common Mode
CH+
CM half circuit
Ф2
CS + Ф2
CH
+
Vo
Ф2
Vo-
CS
-
Vo+
CS Ф2 Vi,cm Acm
CH-
– 39 –
Data Converters Sample-and-Hold Professor Y. Chiu
EECT 7327 Fall 2014
Flip-Around SHA
Ф1 Ф1 Ф1e
CS+ Ф1e Ф2
Vi+ Vo+
Ф2
Vi- Vo-
CS- Ф1e Ф2
Ф1 T H
– 40 –