Operating Systems

Memory Management
Memory Management

• Subdividing memory to accommodate multiple processes

• Memory needs to allocated efficiently to pack as many processes into
memory as possible
Memory Management

• Program must be brought (from disk) into memory and placed

within a process for it to be run.
• Main memory and registers are only storage, CPU can access
directly.
• Register access in one CPU clock (or less).
• Main memory can take many cycles.
• Cache sits between main memory and CPU registers.
• Protection of memory required to ensure correct operation.

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Memory Management

• Background
• Requirements
• Swapping
• Contiguous Memory Allocation
• Paging
• Structure of the Page Table
• Segmentation

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Memory Management Requirements

• Relocation
• programmer does not know where the program will be
placed in memory when it is executed
• while the program is executing, it may be swapped to disk
and returned to main memory at a different location
• memory references must be translated in the code to actual
physical memory address
Memory Management Requirements

• Protection
• processes should not be able to reference memory locations in another process
without permission
• impossible to check addresses in programs since the program could be
relocated
• must be checked during execution
Memory Management Requirements

• Sharing
• allow several processes to access the same portion of memory
• better to allow each process (person) access to the same copy of the program
rather than have their own separate copy
Memory Management Requirements

• Logical Organization
• programs are written in modules
• different degrees of protection given to modules (read-only, execute-only)
• share modules
Memory Management Requirements

• Physical Organization
• memory available for a program plus its data may be insufficient
• overlaying allows various modules to be assigned the same region of memory
• secondary memory cheaper, larger capacity, and permanent
Background

• Input queue – collection of processes on the disk that are

waiting to be brought into memory for execution.

• User programs go through several steps before being run.

• A fundamental task of the memory management component of

an operating system is to ensure safe execution of programs by
providing:
– Sharing of memory
– Memory protection

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Base and Limit Registers
• A pair of base and limit registers define the logical
address space

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Address Binding
• The process of associating program instructions and data
(addresses) to physical memory addresses is called address
binding, or relocation.

• Address binding of instructions and data to memory addresses

can happen at three different stages.

Compile time:
• The compiler or assembler translates symbolic addresses (e. g.,
variables) to absolute addresses.

• If memory location known, absolute code can be generated;

must recompile code if starting location changes.

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Address Binding

Load time:
• The compiler translates symbolic addresses to relative
(relocatable) addresses. The loader translates these to absolute
addresses.

• Must generate relocatable code if memory location is not

known at compile time.

Execution time:

• Binding delayed until run time if the process can be moved

during its execution from one memory segment to another.

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Multistep Processing of a User Program

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From source to executable code

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Address Binding

Functions of a Linker
• A linker collects (if possible) and
puts together all the required pieces
to form the executable code.

• Issues:
• Relocation
where to put pieces.
• Cross- reference
where to find pieces.
• Re- organization
new memory layout.

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Address Binding

Functions of a Loader

• A loader places the executable code in main memory starting at a

pre- determined location (base or start address). This can be done
in several ways, depending on hardware architecture:

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 Logical vs. Physical Address Space

• The concept of a logical address space that is bound to a separate

physical address space is central to proper memory management.

• Logical address – generated by the CPU; also referred to as

virtual address
• Physical address – address seen by the memory unit

• Logical and physical addresses are the same in compile-time and

load-time address-binding schemes; logical (virtual) and physical
addresses differ in execution-time address-binding scheme.

Instructor: M. Rehan Rasheed 18

 Memory-Management Unit (MMU)

• Hardware device that maps virtual to physical address.

• In MMU scheme, the value in the relocation register is added to

every address generated by a user process at the time it is sent to
memory.

• The user program deals with logical addresses; it never sees the real
physical addresses.

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Dynamic relocation using a relocation register

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Dynamic relocation using a relocation register

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Dynamic Loading

• Routine is not loaded until it is called.

• Better memory-space utilization; unused routine is never

loaded.

• Useful when large amounts of code are needed to handle

infrequently occurring cases.

• No special support from the operating system is required

implemented through program design

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Dynamic Linking
• Linking postponed until execution time.

• Small piece of code, stub, used to locate the appropriate

memory-resident library routine
• Stub replaces itself with the address of the routine, and executes
the routine
• Operating system needed to check if routine is in processes’
memory address
• Dynamic linking is particularly useful for libraries

• System also known as shared libraries.

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 Overlays

• Keep in memory only those instructions and data that are

needed at any given time.

• Needed when process is larger than amount of memory

allocated to it.

• Implemented by user, no special support needed from

operating system, programming design of overlay structure is
complex

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Overlays for a Two-Pass Assembler

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 Swapping

• A process can be swapped temporarily out of memory to a backing

store, and then brought back into memory for continued execution.

• Backing store – fast disk large enough to accommodate copies of

all memory images for all users; must provide direct access to these
memory images.

• Roll out, roll in – swapping variant used for priority-based

scheduling algorithms; lower-priority process is swapped out so
higher-priority process can be loaded and executed.

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 Swapping

• Major part of swap time is transfer time; total transfer time is

directly proportional to the amount of memory swapped.

• Modified versions of swapping are found on many systems (i.e.,

UNIX, Linux, and Windows).

• System maintains a ready queue of ready-to-run processes which

have memory images on disk.

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 Swapping (Contd…)

• “if needed, the operating system can always make room for high-
priority jobs, no matter what!”

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Schematic View of Swapping

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 Contiguous Allocation
• Main memory usually into two partitions:
• Resident operating system, usually held in low memory with
interrupt vector.
• User processes then held in high memory.

• Relocation registers used to protect user processes from each other,

and from changing operating-system code and data.
• Base register contains value of smallest physical address
• Limit register contains range of logical addresses – each logical
address must be less than the limit register
• MMU maps logical address dynamically

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Fixed Partitioning

• Main memory use is inefficient. Any program, no matter how small,

occupies an entire partition. This is called internal fragmentation.

Operating System
8M

8M

8M

8M

8M
Fixed Partitioning

• Unequal-size partitions
• lessens the problem with equal-size partitions

Operating System
8M

2M
4M

6M

8M

8M

12 M
Placement Algorithm with Partitions

• Equal-size partitions
• because all partitions are of equal size, it does not matter which partition is
used
• Unequal-size partitions
• can assign each process to the smallest partition within which it will fit
• queue for each partition
• processes are assigned in such a way as to minimize wasted memory within a
partition
One Process Queue per Partition

Operating
System

New
Processes
 One Common Process Queue
• When its time to load a process into main memory the smallest available
partition that will hold the process is selected

Operating
System

New
Processes
Dynamic Partitioning

• Partitions are of variable length and number

• Process is allocated exactly as much memory as
required
• Eventually get holes in the memory. This is called
external fragmentation
• Must use compaction to shift processes so they are
contiguous and all free memory is in one block
Example Dynamic Partitioning

Operating 128 K Operating Operating

System System System

Process 1 320 K Process 1 320 K

Process 2 224 K
896 K

576 K
352 K
Example Dynamic Partitioning

Operating Operating Operating

System System System

Process 1 320 K Process 1 320 K Process 1 320 K

224 K 224 K Process 4 128 K

Process 2
96 K

Process 3 288 K Process 3 288 K Process 3 288 K

64 K 64 K 64 K
Example Dynamic Partitioning

Operating Operating
System System

320 K Process 2 224 k

96 K
Process 4 128 K Process 4 128 K
96 K 96 K

Process 3 288 K Process 3 288 K

64 K 64 K
Dynamic Partitioning Placement Algorithm

• Operating system must decide which free block to

allocate to a process
• Best-fit algorithm
• chooses the block that is closest in size to the request
• worst performer overall
• since smallest block is found for process, the smallest
amount of fragmentation is left memory compaction must
be done more often
Dynamic Partitioning Placement Algorithm

• First-fit algorithm
• starts scanning memory from the beginning and chooses
the first available block that is large enough.
• Next-fit
• starts scanning memory from the location of the last
placement and chooses the next available block that is
large enough
• Compaction is required to obtain a large block at the
end of memory
Hardware Support for Relocation and Limit Registers

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HW address protection with base and limit
registers

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Contiguous Allocation (Cont.)
 Multiple-partition allocation
◦ Hole – block of available memory; holes of various size are
scattered throughout memory
◦ When a process arrives, it is allocated memory from a hole
large enough to accommodate it
◦ Operating system maintains information about:
a) allocated partitions b) free partitions (hole)

OS OS OS OS

process 5 process 5 process 5 process 5

process 9 process 9

process 8 process 10

process 2 process 2 process 2 process 2

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 Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of free holes.

• First-fit: Allocate the first hole that is big enough.

• Best-fit: Allocate the smallest hole that is big enough; must search
entire list, unless ordered by size. Produces the smallest leftover
hole.
• Worst-fit: Allocate the largest hole; must also search entire list.
Produces the largest leftover hole.

First-fit and best-fit better than worst-fit in terms of speed and

storage utilization.

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 Fragmentation
• External Fragmentation – total memory space exists to satisfy a request, but it
is not contiguous.
• Internal Fragmentation – allocated memory may be slightly larger than
requested memory; this size difference is memory internal to a partition, but not
being used.

• Reduce external fragmentation by compaction

• Shuffle memory contents to place all free memory together in one large block
• Compaction is possible only if relocation is dynamic, and is done at execution
time
• I/O problem
• Latch job in memory while it is involved in I/O
• Do I/O only into OS buffers

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 Paging
• Logical address space of a process can be noncontiguous; process is
allocated physical memory whenever the latter is available.
• Divide physical memory into fixed-sized blocks called frames (size
is power of 2, between 512 bytes and 8,192 bytes).
• Divide logical memory into blocks of same size called pages
• Keep track of all free frames.
• To run a program of size n pages, need to find n free frames and
load program.
• Set up a page table to translate logical to physical addresses
• Internal fragmentation.

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 Address Translation Scheme
• Address generated by CPU is divided into:

• Page number (p) – used as an index into a page table which

contains base address of each page in physical memory.
• Page offset (d) – combined with base address to define the
physical memory address that is sent to the memory unit.
Page number Page offset

m–n n

p d

For given logical address space 2m and page size 2n

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Paging Hardware

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Paging Model of Logical and Physical Memory

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Paging Example

32-byte memory and 4-byte pages

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Free Frames

Before allocation After allocation

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Implementation of Page Table

• Page table is kept in main memory.

• Page-table base register (PTBR) points to the page table.

• Page-table length register (PRLR) indicates size of the page

table.

• In this scheme every data/instruction access requires two

memory accesses. One for the page table and one for the
data/instruction.

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Implementation of Page Table

• The two memory access problem can be solved by the use of a

special fast-lookup hardware cache called associative memory
or translation look-aside buffers (TLBs).

• Some TLBs store address-space identifiers (ASIDs) in each

TLB entry – uniquely identifies each process to provide
address-space protection for that process.

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Associative Memory

• Associative memory – parallel search

Page # Frame #

• Address translation (p, d)

• If p is in associative register, get frame # out.

• Otherwise get frame # from page table in memory.

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Paging Hardware With TLB

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Effective Access Time
• The performance of a TLB depends on its hit ratio
• Hit ratio is the percentage of time that a frame number is found in the
TLB

• Associative lookup time is a time units.

• Memory cycle time is m time units.
• Hit ratio is r
• Effective Access Time (EAT) = (m + a) r + (2m + a)(1 – r)

Example
• If a = 20 ns, m = 100 ns, and r = 80%, then
• EAT = (100 + 20) 0.8 + (2(100) + 20)(1 - 0.8) = 140 ns
• For r = 98%, then EAT = 122 ns

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 Memory Protection

• Memory protection implemented by associating protection bit with

each frame.

• Valid-invalid bit attached to each entry in the page table:

• “valid” indicates that the associated page is in the process’

logical address space, and is thus a legal page.

• “invalid” indicates that the page is not in the process’ logical

address space.

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Valid (v) or Invalid (i) Bit In A Page Table

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 Shared Pages
• Shared code
• One copy of read-only (reentrant) code shared among processes
(i.e., text editors, compilers, window systems).
• Shared code must appear in same location in the logical address
space of all processes.

• Private code and data

• Each process keeps a separate copy of the code and data
• The pages for the private code and data can appear anywhere in
the logical address space.

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Shared Pages Example

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Structure of the Page Table

• Hierarchical Paging

• Hashed Page Tables

• Inverted Page Tables

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Hierarchical Page Tables

• Break up the logical address space into multiple page

tables.

• A simple technique is a two-level page table.

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Multilevel Paging

• Modern computers support large logical address spaces (232 to

264).

• With an address space of 232 and a page size of 4k (212), a page

table has one million entries.

• Assuming that each entry is 4 bytes, the page table is 4MB.

• We need an approach to reduce the memory requirements of the

page table.
• One approach is to page the page table

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Multilevel Paging
• A logical address (on 32-bit machine with 4K page size) is
divided into two parts
• 20-bit page number.
• 12-bit frame offset.

• Paging the page table further divides the page number.

• 10-bit page number.
• 10-bit page offset.
• Thus, a logical address is;

• Where p1 is an index into the outer page table, and p2 is the

displacement within the page of the outer page table.

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Two-Level Page-Table Scheme

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Address-Translation Scheme
• Address-translation scheme for a two-level 32-bit paging
architecture

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Three-level Paging Scheme
• Consider a computer with an address space of 264 With a 4k
page and for convenience we make the inner page table fit in
one page (i.e., 210 * 4 bytes), we have

• Even if we page again, we have

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Hashed Page Tables

• Common in address spaces > 32 bits

• The virtual page number is hashed into a page table. This

page table contains a chain of elements hashing to the
same location.

• Virtual page numbers are compared in this chain

searching for a match. If a match is found, the
corresponding physical frame is extracted.

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Hashed Page Table

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 Inverted Page Table
• Another approach to dealing with the resource requirements of page
tables, is inverted page tables.

• One entry for each real page of memory.

• Entry consists of the virtual address of the page stored in that real
memory location, with information about the process that owns that
page.

• Decreases memory needed to store each page table, but increases

time needed to search the table when a page reference occurs.
• Use hash table to limit the search to one -- or at most a few – page-
table entries.

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Inverted Page Table Architecture

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Paging Examples

Assume a page size of 1K and a 15-bit logical address space.

How many pages are in the system?

• Answer: 2^5 = 32.
• Assuming a 15-bit address space with 8 logical pages. How
large are the pages?
• Answer: 2^5 = 32.
• Assuming a 15-bit address space with 8 logical pages. How
large are the pages?
• Answer: 2^12 = 4K. It takes 3 bits to reference 8 logical pages
(2^3 = 8). This leaves 12 bits for the page size thus pages are
2^12.
Consider logical address 1025 and the following
page table for some process P0. Assume a 15-bit
address space with a page size of 1K. What is the
physical address to which logical address 1025
will be mapped?

8
0

2
Consider logical address 1025 and the following
page table for some process P0. Assume a 15-bit
address space with a page size of 1K. What is
the physical address to which logical address
1025 maps?

8 Step 1. Convert to binary:

0 000010000000001

2
Consider logical address 1025 and the following
page table for some process P0. Assume a 15-bit
address space with a page size of 1K. What is
the physical address to which logical address
1025 maps?

Step2. Determine the logical page

8 number:
0 Since there are 5-bits allocated to the
logical page, the address is broken up as
follows:
2
00001 0000000001
Logical page number offset within
page
 Consider logical address 1025 and the following
page table for some process P0. What is the
physical address?

8 Step 3. Use logical page

00001 number as an index into
0 the page table.

2 00001 0000000001
 Consider logical address 1025 and the following
page table for some process P0. What is the
physical address?

8 Take the physical page number from

00001 the page table and concatenate the
0 offset.
The physical address is byte 1.
2 000000000000001
 Segmentation
• Memory-management scheme that supports user view of memory

• A program is a collection of segments; a segment is a logical unit

such as:
• main program,
• procedure,
• function,
• local variables, global variables,
• common block,
• stack,
• symbol table, arrays

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User’s View of a Program

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Logical View of Segmentation

4
1

3 2
4

user space physical memory space

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 Segmentation

• A logical address space is a collection of segments.

• Each segment has a name and a length.

• Addresses specify both the segment name and the offset within the
segment.

• The user specifies two quantities:

• Segment name
• Offset

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 Segmentation Architecture (Cont.)

• Logical address consists of <segment-number, offset>

• Segment table maps two-dimensional physical addresses; each table

entry has;

• base – contains the starting physical address where the segments

reside in memory.

• limit – specifies the length of the segment.

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 Segmentation Architecture (Cont.)

• Segment-table base register (STBR) points to the segment table’s

location in memory.

• Segment-table length register (STLR) indicates number of segments

used by a program

• Segment number s is legal if s < STLR.

• We add the segment number to the STBR, resulting in the

address (STBR + s) in memory of the segment-table entry.

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Segmentation Architecture (Cont.)
• Protection
• With each entry in segment table associate:
• validation bit = 0  illegal segment
• read/write/execute privileges

• Protection bits associated with segments; code sharing occurs

at segment level
• Since segments vary in length, memory allocation is a
dynamic storage-allocation problem
• A segmentation example is shown in the following diagram

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Segmentation Hardware

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Example of Segmentation

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Sharing of Segments

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