16 Sequential Circuits

Sequential Circuits
1. Ways of Describing Sequential Circuits

2. Flip-Flops
3. Registers and Counters
4. Finite State Machines
Sequential Circuits 1
1.1 Definition
1.2 Description
1.1 Definition
X Y CLC Combinational logic circuit

CLC
X Input signals
Y Output signals;
Qn Qn+1 Qn Current state;
Y2
Qn+1 Next state
Memory
The typical structure of the sequential circuit Observation:
X  X1 , X 2 ,, X m 
Y  Y1 , Y2 ,, Yp 
Q  Q1 , Q 2 ,, Q r 
1.1 Definitions (cont.)
Definition: Sequential logic circuit is defined as the

X Y quintuple:
CLC
Qn Qn+1
SS={X, Y, Q ,f, g}
Y2
X set of inputs;
Memory
Y set of outputs;
Q set of states;
The typical structure of the sequential circuit F transition function of the states;
g transition function of the outputs.
X  X1 , X 2 ,, X m 
f : XQ  Q
Y  Y1 , Y2 ,, Yp 
g :XQ  Y or g:Q  Y
Q  Q1 , Q2 ,, Qr 
1.2 Description
Sequential circuits can be represented in three ways:
•transition tables;
•charts;
•flow graphs (transition graphs).
1.2 Description
Transition Table
Input Current State Next State Output
Xn+1 Qn Qn+1 Yn+1
Depending on Depending on Depending on Depending on

the application the application the application the application
1.2 Description
Transition Table
Example: Let’s analyze a machine with two states, two outputs and a single input. In other
words:
Q={0, 1}
X1={0, 1}
X2={0, 1}
Y={0, 1}
The transition table will look like this:
1.2 Description
Transition Table
Input Current State Next State Output

X1,n+1 X2,n+1 Qn Qn+1 Yn+1
0 0 0 1 0
1 0 0 0 1
0 1 0 1 0
1 1 0 1 1
0 0 1 0 0
1 0 1 1 1
0 1 1 0 1
1 1 1 1 0
1.2 Description
Transition Table
•If {X1,X2}={0,0} and Qn=0 then Qn+1=1 and Y=1 (line 1)

1.2 Description
Chart
Only transitions starting from “0” state are presented
•If Qn=0 and {X1,X2}={0,0} then Qn+1=1 and Y=1

1.2 Description
Flow Grafs
Flow graf associated with transition from state "0" to "1“
2. Flip-Flops
2.1 RS Flip-Flop
2.2 D Flip-Flop
2.3 JK Flip-Flop
2.1 RS Flip-Flop
2.1.1 RS Latch
2.1.2 Latch RS Latch
2.1.3 Gated RS Latch
2.1 RS Flip-Flop
2.1.1 RS NOR Latch
a.) Symbol
RS Latch ANSI standard RS Latch DIN standard
b.) Notation
R, S Data inputs
Q, Q Data outputs
2.1 RS Flip-Flop
2.1.1 RS NOR Latch
c.) Schematic Diagram
d.) Operation
Inputs Output
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
Truth table for NOR gate type
2.1 RS Flip-Flop
2.1.1 RS NOR Latch
d.) Operation
Input Next State

Comments
Sn Rn Qn+1 Q n+1
0 0 Qn Qn Hold state
0 1 1 Set
0 1 0 1 Reset
1 1 0 0 Not allowed
Simplified transition table for the RS NOR latch
2.1 RS Flip-Flop
2.1.1 S Latch
d.) Operation
Inputs Next State

Comments
Sn Rn Qn+1 Q n+1
1 0 1 0 Set
0 1 0 1 Reset
1 1 1 0 Set
Simplified transition table for the S latch
2.1 RS Flip-Flop
2.1.1 R Latch
d.) Operation
Inputs Next Stage

Comments
Sn Rn Qn+1 Q n+1
1 0 1 0 Set
0 1 0 1 Reset
1 1 0 1 Reset
Simplified transition table for the R latch
2.1 RS Flip-Flop
2.1.1 E Latch
d.) Operation
Inputs Next Stage

Comentarii
Sn Rn Qn+1 Q n+1
1 0 1 0 Set
0 1 0 1 Reset
Simplified transition table for the E latch
2.1 RS Flip-Flop
2.1.1 RS Latch
e.) SPICE Simulation
Circuit used to simulate the Waveforms associated with the operation of a RS latch
operation of a RS latch
2.1 RS Flip-Flop
2.1.1 RS Latch
The analysis of the waveforms must be made taking into account two objectives:
i. ”When” Analysis - when the transitions occur;
ii. ”How” Analysis - how transitions occur.
i.) ”When” Analysis Waveform analysis reveals that the output transitions are controlled by signals
applied to the inputs R and S – times t1 – t6.
ii.) ”How” Analysis Waveform analysis reveals that:

_ interval t1 – t2 S=1; R=0 Q=1 Q=0;
_ interval t2 – t3 S=0; R=0 Q=1 Q=0;
_ interval t3 – t4 S=0; R=1 Q=0 Q=1;
_ interval t4 – t5 S=0; R=0 Q=0 Q =1;
_ interval t5 – t6 S=0; R=0 Q=0 Q =1.
Conclusion: The results presented confirm the transition table.

2.1 RS Flip-Flop
2.1.2 RS Latch
a.) Symbol
Latch RS Latch ANSI standard RS Latch DIN standard
b.) Notation
R, S Data inputs.
Q, Q Outputs
2.1 RS Flip-Flop
2.1.2 RS Latch
c.) Schematic diagram
d.) Operation
Inputs Output
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
Truth table for NAND gate
2.1 RS Flip-Flop
2.1.2 RS Latch
d.) Operation
Inputs Next State

Comments
Sn Rn Qn+1
0 0 Qn+1= Q n+1=1 Not allowed
1 0 1 Set
0 1 0 Reset
1 1 Qn Hold state
Simplified transition table for the R S latch
2.1 RS Flip-Flop
2.1.2 RS Latch
Circuit used to simulate the Waveforms associated with the operation

operation of a R S latch of a R S latch
2.1 RS Flip-Flop
2.1.2 RS Latch
i.) ”When” Analysis Waveform analysis reveals that the output transitions are controlled by
signals applied to the inputs ~R and ~S – times t1 – t5.
.
ii.) ”How” Analysis Waveform analysis reveals that: :
_ interval t1 – t2 S =1; R =0 Q=0 Q =1;
_ interval t2 – t3 S =1; R =1 Q=0 Q =1;
_ interval t3 – t4 S =0; R =1 Q=1 Q =0;
_ interval t4 – t5 S =1; R =1 Q=1 Q =0.
Note: The results presented confirm the transition table associated with latch operation
The latch does not make a distinction between "when“ and "how”
2.1 RS Flip-Flop
a.) Symbol
Gated RS Latch ANSI standard Gated RS Latch DIN standard

b.) Notation
R, S Data input
QQ Output
EN Enable
2.1 RS Flip-Flop
c.) Circuit Diagram
Gated RS Latch - circuit diagram
2.1 RS Flip-Flop
d.) Operation
Inputs Next State

Comments
EN Sn Rn Qn+1
0 X X Qn Hold state
1 0 0 Qn Hold state
1 1 0 1 Set
1 0 1 0 Reset
1 1 1 Qn+1= Q n+1=0 Not allowed
2.1 RS Flip-Flop
•“When" Analysis: Waveform analysis reveals that the output transitions occur if EN = logical "1" (the
interval t1 - t2). In other words, transitions occur on the level of gate pulse.
• “How" Analysis: Waveform analysis reveals that the output transitions are controlled by signals
applied to the inputs R and S.
2.2 D Flip-Flop
2.2.1 D Latch
2.2.2 Gated D Latch
2.2.3 D Flip-Flop
2.2 D Flip-Flop
2.2.1 D Latch
a.) Symbol
D Latch ANSI standard D Latch DIN standard
b.) Notation
D Data inputs
Q, Q Outputs
2.2 D Flip-Flop
2.2.1 D Latch
c.) Circuit diagram
d.) Operation
Input Current State Next State
Comments
Dn Qn Qn+1
0 X 0 Reset
1 X 1 Set
2.2 D Flip-Flop
2.2.1 D Latch
„When” Analysis: Waveform analysis reveals that the output transitions are controlled by the
signal applied to the D input - (see times t1, t2 and t3)
„How” Analysis: Waveform analysis reveals that :
interval t1 – t2 D=1 Q=1 Q =1
interval t2 – t3 D=0 Q=0 Q =0
2.2 D Flip-Flop
2.2.2 Gated D Latch
a.) Symbol
Gated D Latch D ANSI standard Gated D Latch D DIN standard
b.) Notation
D Data input.
EN Enable. Transitions between states can occur where EN = 1
QQ Outputs
2.2 D Flip-Flop
2.2.2 Gated D Latch
c.) Circuit diagram
d.) Operation
Input Next State

Comments
EN Dn Qn+1
0 X Qn Hold state
1 1 1 Set
1 0 0 Reset
2.2 D Flip-Flop
2.2.2 Gated D Latch
„When” Analysis: Waveform analysis reveals that the output transitions occur if EN = logical "1"
(the interval t2 - t3). In other words, transitions occur on the level of the clock pulse
„How” Analysis: Waveform analysis reveals that the output transitions are controlled by the
signal applied to the input D
D-type latch with gate does not make a distinction between "when” and "how" (how are these
transitions).
2.2 D Flip-Flop
2.2.3 D Flip-Flop
•D flip-flop switching on positive edge (transition "0" to "1“)
•D flip-flop switching on positive edge (transition "0" to "1“)
2.2 D Flip-Flop
2.2.3 D Flip-Flop
D flip-flop switching on positive edge (transition "0" to "1“)
a.) Symbol
ANSI Standard DIN Standard
b.) Notation
D Data input
CLK CLOCK
QQ Output
2.2 D Flip-Flop
2.2.3 D Flip-Flop
c.) Operation
Inputs Outputs
Comments
CLK D Qn+1 Q n+1
↑ 1 1 0 Set
↑ 0 0 1 Reset
0 X Qn Q n Hold state
1 X Qn Q n Hold state
↓ X Qn Q n Hold state
Simplified transition table
2.2 D Flip-Flop
2.2.3 D Flip-Flop
d.) SPICE Simulation
„When” Analysis: Waveform analysis reveals that the output transitions occur on the positive
edge of the clock pulse (times t1 and t2).
Time t1; D=1 Q=1 Q =0
Time t2; D=0 Q=0 Q =1
D flip-flop switching on positive edge of the clock pulse makes a clear distinction between "when”
and "how“
2.2 D Flip-Flop
2.2.3 D Flip-Flop
D flip-flop switching on negative edge (transition "0" to "1“)
a.) Symbol
ANSI Standard DIN Standard

b.) Notatii folosite
D Data input
CLK CLOCK
QQ Output
2.2 D Flip-Flop
2.2.3 D Flip-Flop
c.) Operation
Inputs Outputs
Comments
CLK D Qn+1 Q n+1
↓ 1 1 0 Set
↓ 0 0 1 Reset
0 X Qn Qn Hold state
1 X Qn Qn Hold state
↑ X Qn Q
n Hold state
2.2 D Flip-Flop
2.2.3 D Flip-Flop
d.) SPICE Simulare
„When” Analysis: Waveform analysis reveals that the output transitions occur on the negative
edge of the clock pulse (times t1 and t2)
Time t1; D=1 Q=1 Q =0
Time t2; D=0 Q=0 Q =1
D flip-flop switching on negative edge of the clock pulse makes a clear distinction between "when“
and "how“
2.3 JK Flip-Flop
Previously, RS flip-flop was presented. Analysis of this flip-flop revealed that a certain combination
of inputs, namely R = S = 1 is not allowed. D flip-flop presented a possible solution to avoid this
limitation. Another solution is the JK flip-flop. This type of solution implies the introduction of a new
level of internal reaction. Thus, the internal structure of such a flip-flop becomes:
Inputs Next state

Comments
Jn Kn Qn+1
0 0 Qn Hold state
1 0 1 Set
0 1 0 Reset
1 1 Qn Change state
Circuit diagram Transition table
2.3 JK Flip-Flop
Note There are four types of JK flip-flops. Namely they are:
JK flip-flop switching on positive edge of the clock pulse and RS asynchronous active inputs
JK flip-flop switching on positive edge of the clock pulse and RS asynchronous active inputs
JK flip-flop switching on negative edge of the clock pulse and RS asynchronous active inputs
JK flip-flop switching on negative edge of the clock pulse and RS asynchronous active inputs
3. Registers and Counters
3.1 Registers
3.2 Counters
3.1 Registers
a.) Definition
Digital circuit consisting of several flip-flops connected so that they can perform certain
operations such as storing multiple bits simultaneously (digital word), or the ability to "move" the
information contained in a digital word.
Observation
'Movement' of information means specific procedures such as "shift left" and “shift right"
shift left shift right
3.1 Registers
b.) Classification
Memory Register - group of BIST able to be write or read simultaneously. Important to note is that
all four flip-flops that have the same clock signal (CLK)
Register Files - groups of flip-flops, that may be addressed (read or write) by a digital word.
Shift register - Bist group that have the ability to move information between different BIST
existing
I/O Registers - used in parallel-series or series-parallel conversion
Series-parallel conversion Series-parallel conversion Parallel-series conversion

shift left shift right
3.2 Counters
a.) Definition
The counter is a digital circuit - consisting of several BIST - able to perform only certain
well-defined sequence of states with no additional conditions for the transition between
states
b.) Classification
The literature presents several ways of classifying according to:
•The mechanism of transition between states (analysis of "when")

•Asynchronous counters
•Synchronous counters
•Ordering of states (analysis of "how").
•decimal
•binary
•Gray
3.2 Counters
b.) Classification (cont.) Depending on the mechanism of transition:
Asynchronous counters
Synchronous counters
3.2 Counters
b.) Classification (cont.) According to states ordering there are:
•Binary counter, Gray counter, decade counter, ring counter or Johnson counter.
•Up/down counter
3.2 Counters
b.) Classification (cont.)
Decimal Binary State
State QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
Binary counter
3.2 Counters
b.) Classification (cont.)
Graph associated with the Graph associated with the operation

operation of the four-bit binary of the four-bit binary counter
counter counting upwards counting downwards
3.2 Counters
b.) Classification (cont.) Gray Counter
Stare Stare binar
zecimal QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 1
3 0 0 1 0
4 0 1 1 0
5 0 1 1 1
6 0 1 0 1
7 0 1 0 0
8 1 1 0 0
9 1 1 0 1
10 1 1 1 1
11 1 1 1 0
12 1 0 1 0
13 1 0 1 1
14 1 0 0 1
15 1 0 0 0
Gray Counter
3.2 Counters
b.) Classification (cont.) Gray Counter
Graph associated with the operation of Gray Counter
3.2 Counters
b.) Classification (cont.) Decade counter
Stare Stare binar

zecimal QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
3.2 Counters
b.) Classification (cont.) Decade counter
Graph associated with the operation Graph associated with the operation
of four bit decimal counter counting of four bit decimal counter counting
upwards downwards
3.2 Counters
b.) Classification (cont.) Ring counter
Decimal Binary (state)

(state) QD QC QB QA
0 0 0 0 1
1 0 0 1 0
2 0 1 0 0
3 1 0 0 0
3.2 Counters
b.) Classification (cont.) Ring counter
Graph associated with the ring counter, upwards

counting
3.2 Counters
b.) Classification (cont.) Jhonson Counter
Decimal Binary (state)

(state) QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 1
3 0 1 1 1
4 1 1 1 1
5 1 1 1 0
6 1 1 0 0
7 1 0 0 0
3.2 Counters
b.) Classification (cont.) Numărătorul de tip Jhonson
Graph associated with Jhonson four bit counter

counting upwards

16 Sequential Circuits

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16 Sequential Circuits

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Sequential Circuits

1. Ways of Describing Sequential Circuits

X Y CLC Combinational logic circuit

The typical structure of the sequential circuit Observation:

Definition: Sequential logic circuit is defined as the

Sequential circuits can be represented in three ways:

Input Current State Next State Output

Xn+1 Qn Qn+1 Yn+1

Depending on Depending on Depending on Depending on

Input Current State Next State Output

•If {X1,X2}={0,0} and Qn=0 then Qn+1=1 and Y=1 (line 1)

•If Qn=0 and {X1,X2}={0,0} then Qn+1=1 and Y=1

Flow graf associated with transition from state "0" to "1“

2.1.2 Latch RS Latch

2.1.3 Gated RS Latch

RS Latch ANSI standard RS Latch DIN standard

Truth table for NOR gate type

Input Next State

Simplified transition table for the RS NOR latch

Inputs Next State

Simplified transition table for the S latch

Inputs Next Stage

Simplified transition table for the R latch

Inputs Next Stage

Simplified transition table for the E latch

ii.) ”How” Analysis Waveform analysis reveals that:

Conclusion: The results presented confirm the transition table.

Latch RS Latch ANSI standard RS Latch DIN standard

Inputs Next State

0 0 Qn+1= Q n+1=1 Not allowed

Simplified transition table for the R S latch

Circuit used to simulate the Waveforms associated with the operation

Gated RS Latch ANSI standard Gated RS Latch DIN standard

Gated RS Latch - circuit diagram

Inputs Next State

2.2.2 Gated D Latch

D Latch ANSI standard D Latch DIN standard

Gated D Latch D ANSI standard Gated D Latch D DIN standard

Input Next State

•D flip-flop switching on positive edge (transition "0" to "1“)

•D flip-flop switching on positive edge (transition "0" to "1“)

ANSI Standard DIN Standard

Simplified transition table

ANSI Standard DIN Standard

Inputs Next state

Circuit diagram Transition table

shift left shift right

I/O Registers - used in parallel-series or series-parallel conversion

Series-parallel conversion Series-parallel conversion Parallel-series conversion

The literature presents several ways of classifying according to:

•The mechanism of transition between states (analysis of "when")

Graph associated with the Graph associated with the operation

Graph associated with the operation of Gray Counter

Stare Stare binar

Decimal Binary (state)

Graph associated with the ring counter, upwards

Decimal Binary (state)

Graph associated with Jhonson four bit counter

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