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photoresist
silicon dioxide
silicon •Wafer is covered with photoresist
photomask
photoresist •A photomask is placed on wafer
silicon dioxide
silicon
Semiconductor Manufacturing Steps
UV radiation
photomask
photoresist •Wafer is exposed to ultra-violet
silicon dioxide
silicon (UV) radiation
photoresist
silicon dioxide •Unexposed regions dissolved
silicon
photoresist
silicon dioxide •Unprotected oxide etched
silicon
silicon dioxide
doped regions •Doping creates n or p-type wells
VOUT
Vi1 M1 M2
Vi2
VOUT
Vi1 W1=300m
W2=300m
Vi2
VOUT
Vth1=0.7V
Vi1 Vth2=0.7V
Vi2
VOUT
Id1=1mA
Vi1 Id2=1mA
Vi2
W1 W2 G
Nominal :
VOUT 300 300 100
PVE+RE
causing mismatch:
Vi1 300 300
303 303 303 102
Vi2 297 297 98
PVE+RE not
causing mismatch:
Iref
300+2+-2 300+2+1 303 300 99
297 300 90
PVE RE PVE RE G G
Manual design
SPICE simulations
Optimizations
Manual design
SPICE simulations
Optimizations
Optimizations
Test & diagnosis after production Models for Test and diagnosis
Worst-Case Estimations Fail in Deep Sub-Micron
Bandgap
reference actual pdf
circuit
Vb1
Vb2
Iref Vb3 99 %
falls in
Worst-case limits for this range
an output parameter OpAmp
Iref
Current mirror
PVE
A B A B B A
tox=4.2nm tox=4.2nm
tox=4.1nm tox=4.1nm
tox=4.0nm
tox=4.0nm
A B B A
tox=4.2nm
tox=4.1nm
tox=4.0nm
Thermometer Encoder
DAC
1-Bit y2[n]
b DAC y[n]
x[n] .
. . y[n]
.
1-Bit
x2b[n] DAC y2b [n]
x[n]
PSD
•The circuit implements an ideal staircase
transfer function between input and output
•Mismatch within DAC’s cause a related frequency
performance parameter, PSD, to fail specifications
I. Galton and P. Carbone, “A Rigorous Error Analysis of D/A
Conversion with Dynamic Element Matching,” IEEE TCAS-II, 1995
Circuit Optimizations
A Low Harmonic DAC
PSD
x1[n] 1-Bit y1[n]
Thermometer Encoder
DAC
1-Bit y2[n]
DAC
Scrambler
x[n] b
.
. . . y[n] frequency
. .
1-Bit
x2b[n] DAC y2b [n]
Thermometer Encoder
DAC
. 1-Bit y2[n]
. DAC
Scrambler
x[n] b
. . y[n]
. . frequency
1-Bit
x2b[n] DAC y2b [n]
Thermometer Encoder
DAC
. 1-Bit y2[n]
. DAC
Scrambler
x[n] b
. . y[n]
. .
1-Bit
x2b[n] DAC y2b [n]
+
ID1 ID2
+
I D1R1 I D2 R2
VGS1 VGS2 Drain current formula:
Vos - -
1 W
I D nCox VGS Vth
2
Iref
2 L
Differential stage
WL
•Variance of deviation in a parameter is inversely
proportional to the area of the transistors to be matched
f ( x, y) a( x y ) bx cy d
2 2
x
•Parameters (x,y) formulated using integration over pairs’ areas
•A covariance matrix for (x,y) is formulated using Gaussians as
an autocorrelation function
•Levenberg-Marquardt least squared method used to fit
parameters in the formulations to on-chip measurement data
M. Conti, P. Crippa, S. Orcioni and C. Turchetti, “Layout-
Based Statistical Modeling for the Prediction of the Matching
Properties of MOS Transistors,” IEEE TCAS-I, 2002
Incorporation of Effective Lengths
•Suggestion of usage of effective width and lengths instead, as
dotted effective area important for matching
M1 M2 equal initial areas
for MOS channels
transistor channels (solid lines)
•Equal nominal mask areas for differing transistor shapes may
result in mismatch when lengths in real chip are considered
•If L is nominal, L-L is the effective length caused by penetration
of doping under channel region L
Leffective
•Algebraic estimation of L is possible using SPICE models
•Pelgrom’s equation used with effective lengths of transistors
N ,M
Cnm
(P)
2
Cnm : fitting constants
n,m (Wn W ) n
( Lm L ) m
Ap2
2 (P) S p2 Dx2
WL
|13| MN sP DMN
|23|
|12| P2 DMN : distance between transistors
P1 A32 R2
A22 sp : fitting constant
•Once P1 is fixed to origin, location of other transistors are found
using geometry, then Aij values can be extracted on the axes
•-space analysis relates variances in parameters to distances
between transistors thus preserving space correlations
C. Michael and M. Ismail, “Statistical Modeling of Device
Mismatch for Analog MOS Integrated Circuits,” JSSC, 1992
Principal Component Analysis (PCA) for
Preserving Correlations
P p •Normalize each parameter
P`
p P,Q : parameters
P` : normalized parameter
1 n
ρPQ i 1 P`Qi ` •Find correlations
n
•Apply PCA by finding
1/ 2 1
C U P` eigenvalues and eigenvectors
of C first
P` U C 1/ 2 C : principal component vector
: diagonal eigenvalue matrix
U : eigenvector matrix
P` : normalized parameter matrix
•PCA helps preserve parameter correlations by writing each
parameter as a function of independent principal components
C. Michael and M. Ismail, “Statistical Modeling of Device
Mismatch for Analog MOS Integrated Circuits,” JSSC, 1992
An Example of PCA Application
•PCA helps formulate normalized parameters in terms of
independent principal components:
P` U C 1/ 2
delvt Vth x1
+Considers layout
+Considers correlations
-Correlation constants are somewhat inaccurate themselves
-Requires fitting and process related constants
-Does not provide an intuitive understanding of mismatch
-Parameter inaccuracies due to extraction from wafer may be
magnified through PCA
Outline
i pi
e variances of physical parameters
e : electrical parameter
p : physical parameter
•pi’s are dependant on size and distance of transistors
•pi’s can be Vfb, Tox, W, L, 0, Nsub, etc.
•If enumeration factors are such that |e| > |i|, estimation of physical
parameter variances from electrical measurements is also possible
•Due to complex formulas, CAD tools required
P. G. Drennan and C. C. McAndrew, “Understanding
MOSFET Mismatch for Analog Design,” JSSC, 2003
An Tractable Physics-based Mismatch Model
•Random effects mimicked through assigning pdf’s to Level0 parameters
Independent
W L NSUB VFB n tox Level0 Normal
Correlated?
Vth Cox Level1 pdf?
Correlated?
k Each node is a parameter Level2 pdf?
Correlated?
gm
Level4 pdf?
R. O. Topaloglu and A. Orailoglu, “Mismatch in the Deep
Sub-Micron Era : From Physics to Circuits,” ASP-DAC, 2004
Connectivity Based Traversal
•Proposed approach provides a manually tractable estimation
•Chain rule used to relate a high level parameter to physical ones
L0 : level 0 x y
L0 NSUB Sy
x
y x
VT0=f1(NSUB) PHI
L1
L2 VT0 VT0=f2(PHI,NSUB)
Vth=f3(PHI,VT0)
Vth L3
L0 NSUB
VT0=f1(NSUB) PHI
L1
L2 VT0 VT0=f2(PHI,NSUB)
Vth=f3(PHI,VT0)
Vth L3
L0 NSUB
VT0=f1(NSUB) PHI
L1
L2 VT0 VT0=f2(PHI,NSUB)
Vth=f3(PHI,VT0)
Vth L3
Vth L5
Id L6
design parameters gm L7
circuit parameters rout CMRR L8
Critical Analysis of Physics-based Mismatch
Modeling
Iref
~Gaussian
G1
G3
G2
Iref
non-Gaussian
G3
G2
Iref
non-Gaussian
G1