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Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
Design
Methodologies
December 10, 2002
Productivity (Trans./Staff-Month)
Logic Transistors per Chip (K)
1,000 10,000
X
100 X X
1,000
X x X
X
2.5m 10 21%/Yr. compound 100
Productivity growth rate
Logic Transistors
1 per Chip (K) 10
Produc
1981
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1991
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1995
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1999
2001
2003
2005
2007
2009
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2003
2005
2007
2009
A growing gap between design complexity and design productivity
Source: sematech97
MEMORY
INPUT/OUTPUT
CONTROL
INPUT-OUTPUT
DATAPATH
Courtesy: Philips
Domain-specific processor
100-1000
Energy Efficiency (in MOPS/mW)
Embedded microprocessor
10-100
(e.g. DSP)
Configurable/Parameterizable
Hardwired custom
1-10
0.1-1
Custom Semicustom
Cell-based Array-based
Routing channel
requirements are
reduced by presence
of more interconnect
layers
[Brodersen92]
Cell-structure
hidden under
interconnect layers
x0 x1
x2
AND OR
plane plane
f0 f1
x0 x1 x2
minterm
x0 x0 x1 x1 x2 x2 f0 f1
Pull-up devices Pull-up devices
BUFFER
BUFFER PRE-CHARGE
CHARGE
BUFFER
PRE-
BUFFER PRE-CHARGE
PRE-CHARGE
BUFFER
BUFFER PRE-CHARGE
BUFFER
PRE-
BUFFER PRE-CHARGE
• Output buffers and the input buffers
of the next stage are shared.
Area:
RPLAs (2 layers) 1.23
SCs (3 layers) - 1.00, 1
NPLAs (4 layers) 1.31
Delay
RPLAs 1.04
SCs 1.00
0.6
NPLAs 1.09
Synthesis time: for RPLA , synthesis time equals design time;
SCs and NPLAs still need P&R.
Also: RPLAs are regular and predictable
0.2
0 2 4 6 area
HDL
Pre-Layout
Structural
Design Iteration
Simulation
Logic Synthesis
Floorplanning
Post-Layout
Simulation Placement Physical
Tape-out
Physical Synthesis
Place-and-Route
Optimization
Artwork
© Digital Integrated Circuits2nd Design Methodologies
Late-Binding Implementation
Array-based
Pre-diffused Pre-wired
(Gate Arrays) (FPGA's)
polysilicon
VD D
metal
rows of Uncommited
uncommitted possible
cells GND contact Cell
routing
channel Committed
Cell
(4-input NOR)
Out
PMOS
PMOS
NMOS
NMOS
NMOS
Random Logic
Memory
Subsystem
Via-programmable cross-point
metal-5 metal-6
programmable via
n+ antifuse diffusion
2l
: programmed node
NA NA f 1 f 0
B 1
SA Y
1
C
D 1
SB
S0
S1
In Out
Memory
Out 00 00
01 1
10 1
11 0
ln1 ln2
D4 Bits xxxx
Logic control
D3 xx xx
function xx
xx x xx x
D2 of xx
xxx
D1
Logic xx xx
functionx x
x
of x x
F4 xxx
Bits xxxx
F3 Logic xx control xx
function xx
xx x xx x
F2 of xx
xxx
F1
xx xx
x
xxxxx x
H x
P
Multiplexer Controlled
by Configuration Program
Xilinx 4000 Series
Cell
Horizontal
tracks
Vertical tracks
Connect Box
Interconnect
Point
t PIA
LAB1 LAB2
LAB
PIA
t PIA
LAB6
Array-based Mesh-based
(MAX 3000-7000) (MAX 9000)
Program/Test/Diagnostics
Vertical routes
Standard-cell like
floorplan
I/O Buffers
I/O Buffers
Rows of logic modules
Routing channels
I/O Buffers
12 Quad
8 Single
4 Double
3 Long
Direct
CLB 2 Connect
3 Long
12 4 4 8 4 8 4 2
Xilinx XC4000ex
600k transistors
208-pin PGA
fclock = 50 MHz
Pav = 3.6 W @ 5V
Analog
Multi-
Spectral
RAM + 1 Gbit DRAM where cost, performance,
Imager Preprocessing and energy are the real
64 SIMD Processor issues!
mC
Array + SRAM system DSP and control intensive
+2 Gbit Mixed-mode
Image Conditioning DRAM Combines programmable
100 GOPS Recog-
and application-specific
nition
modules
Software plays crucial role
© Digital Integrated Circuits2nd Design Methodologies
Addressing the Design Complexity Issue
Architecture Reuse
Embedded memories
Embedded PowerPc
Hardwired multipliers
High-speed I/O