MMIC Layout Review

57 – 64 GHz LNA 90-nm CMOS

Student: R06942013 楊易儒 D06943004 吳源深

F04525034 林書辰 A07943201 Andries Deroo

Date: 3th January, 2019

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 Outline
 Project Motivation
 Circuit Architecture
 Response to action items
 Design flow
 Summary of simulation vs design goals
 Layout
 Future work
 Work distribution
 Reference

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 Project Motivation
In order to achieve a low noise and wideband amplifier (57 ~ 67 GHz), applied for the
5𝑡ℎ generation communication system to make it a perfect wide bandwidth and short
range high data-rate. We want to choose an architecture from these papers to achieve
our design goal.

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 Response to action items
 Show bypass capacitor in the schematic
 Don’t use ideal inductance with series resistance of 0.1 Ohm in simulations
 Use same presentation order as the design flow
 Increase the gain flatness for frequencies above 60GHz
 In third stage, show how we implement AC short
 In third stage, show that Vds will not exceed breakdown voltage
 Besides 50 Ohm matching, try inter-stage matching

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Design flow
Start from lumped
a
component model

Replace each stage Simulate and optimize

a the final value
with Sonnet layout

Combine each
a
stage together
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 First Stage
Transistor Capacitor [fF] Inductor [pH]
/Resistor
3.3V thick oxide Vout M2 W:3 u *8 C11 300 L11 110.8
L: 100 n C12 32.5 L12 112
C13 49 LD1 143
LS2 40

 Using 0.1 Ohm setup:

 Gain: 6.19 dB
 NF: 3.85 dB
 Using Q factor = 20 setup:
 Gain: 5.3 dB
 NF: 4.37 dB
 Using EM result:
 Gain: 5.2 dB
 NF: 4.4 dB 6
1st stage Testbench

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1st stage : S11 and S22

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1st stage : NF, Gain and Stability

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 Second Stage
Transistor Capacitor [fF] Inductor [pH]
/Resistor
M2 W:3 u *8 C21 49.8 LG1 133
L: 100 n C22 40 LD2 157
LS2 40

 Using 0.1 Ohm setup:

 Gain: 6.27dB
 NF: 4.06 dB
 Using Q factor = 20 setup:
 Gain: 5.1 dB
 NF: 4.53 dB
 Using EM result:
 Gain: 5.1 dB
 NF: 4.58 dB
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2nd stage Testbench

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2nd stage : S11 and S22

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2nd stage : NF, Gain and Stability

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 Third Stage
Transistor Capaci [fF] Inductor [pH]
/Resistor tor
M3, M4 W:3 u *12 C31 63.03 L31 182
L: 100 n C32 41.57 Ld3 149
Ls3 20
1.5 V

 Using 0.1 Ohm setup:

0.88 V  Gain: 11.59 dB
 NF: 6.15 dB
 Using Q factor = 20 setup:
 Gain: 10 dB
 NF: 6.7 dB
 Using EM result:
 Gain: 9.4 dB
 NF: 6.7 dB
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3rd stage : S11 and S22

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3rd stage : NF, Gain and Stability

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Overall architecture

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Overall: S11 and S22

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Overall Gain, NF, Stability

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 Matching comparison

Blue (VB_all_1_2_3): conjugate matching in inter-stage with lumped component

Red: current design with lumped component
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 Summary of simulation vs design goals
Design Goal Lumped Circuit results Layout results
Frequency [GHz] 60 60 60
Power Gain [dB] >20 23.45 19.4
Bandwidth [GHz] 57-66 52-63.9 51.4-65.7
Noise Figure [dB] <4.5 4.65 5.4
S11 : <-10 (53-64.3) S11 : <-10 (47-60.4)
I/O RL [dB] < -10
S22 : < -10 (58.6-62.8) S22 : < -10 (60-65)
1 (1st stage, 2nd stage) 1 (1st stage, 2nd stage)
Supply Voltage [V] 1.5
1.5 (3rd stage) 1.5 (3rd stage)

Power Consumption [mW] < 20 23 23

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 Layout: 1ST Stage
 Schematic View for LVS  M9 resistor as self-made inductor in LVS  Layout View

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 Layout: 2nd Stage
 Schematic View for LVS  M9 resistor as self-made inductor in LVS  Layout View

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 Layout: 3d Stage
 Schematic View for LVS  M9 resistor as self-made inductor in LVS  Layout View

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Total Layout

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Full LVS

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Full DRC
DRC error has not fixed
1. Density Error
2. Error due to no sealring
3. VIA8 (caused in self-made
inductor)

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 Future work
 Replace the spiral inductors with transmission lines.
 Flatten the gain and make the Output matching better.
 Make the LNA in differential topology to increase the gain and make the noise better.
 Find a new topology to make the differential LNA with low power consumption.

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 Work distribution
 Paper survey: Everyone
 Pre-simulation Lumped Layout:吳源深
 Layout of needed components:楊易儒, Andries Deroo, 林書辰

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 Reference
[1] C.H.Doan, S.Emami, A.M.Niknejad, and R.W.Brodersen, “Millimeterwave CMOS
design,” IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 144 – 155, Jan. 2005.
[2] Yao, T., Gordon, M.Q., Tang, K.K.W., Yau, K.H.K., Yang, M.-T., Schvan, P., and
Voinigescu, S.P.: ‘Algorithmic design of CMOS LNA and PAs for 60-GHz radio’, IEEE J.
Solid State Circuits, April 2007, pp. 1044–1057
[3] M. Kraemer, D. Dragomirescu, et R. Plana, " A low-power high-gain LNA for the 60
GHz band in a 65 nm CMOS technology ", Asia Pacific Microwave Conference, Singapore,
Singapore: 2009, pp. 1156- 1159.
[4] C. Wang, Y. Hao, et al, “A 60GHz LNA with 4.7dB NF and 18dB gain using interstage
impedance matching technique in 90nm CMOS,” IEEE Int. Conf. on Microwave
Technology & Computational Electromagnetics, pp. 270–273, 2011.
[5] K. Kang, J. Brinkhoff, and F. Lin, “A 60GHz LNA with 18.6 dB gain and 5.7 dB NF in
90nm CMOS,” IEEE Int. Conf. on Micro. & Millimeter Wave Tech, May 2010 30
The END

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 Passive Comoponent

Results with sonnet layout Results with lumped component

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 Passive Comoponent

Results with sonnet layout Results with lumped component

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 Passive Comoponent

Results with sonnet layout Results with lumped component

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 Passive Component

Cap : 24.49 fF Cap : 34.11 fF

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 Passive Component

Cap : 306.1 fF
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 Passive Component

Ind : 20 pH Ind : 40.7 pH

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 Passive Component

Ind : 111.8 pH Ind : 133.1 pH

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 Passive Component

Ind : 143.3 pH Ind : 149 pH

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 Passive Component

Ind : 162.1 pH Ind : 183 pH

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