You are on page 1of 55

240-208

Fundamental of Computer
Architecture

November 01, 2003 By Panyayot Chaikan


panyayot@coe.psu.ac.th
Chapter 3
The Processing Unit

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 2


Computer BUS
◆A group of wires that connects
several devices
◆ Three types of Bus
◆ Address bus
◆ Data bus
◆ Control bus

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 3


Address bus
◆ Used to specify memory location that the cpu want to access(read/write)
◆ n-bit address bus provides 2n addresses
◆ For Example
◆ MCS-51 16-bit address bus -> 216 = 16 Kbyte of memory
◆ 8086 20-bit address bus -> 220 = 1 Mbyte of memory
◆ Pentium 32-bit address bus -> 232 = 4 Gbyte of memory

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 4


Databus
◆ Used to sent data between CPU and
peripheral(memory, i/o)
◆ The more bit of data bus, the more speed
achieved
◆ For Example
◆ MCS-51 8-bit data bus
◆ 8086 16-bit data bus
◆ Pentium 64-bit data bus

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 5


BUS
Data bus
Microprocessor

ROM

RAM

I/O
Address bus

C ontrol bus

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 6


CPU : Basic operations
◆ Fetch : Read the instructions and data from memory
◆ Execute : perform the desired operation and write the
result into the memory or registers

Fetch Execute Fetch Execute Execute


Fetch

Instruction Cycle

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 7


C P U
FETCH

R 0
240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 8
M

1 0 0 0 0
240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 9
Terminology
◆ IR : Instruction Register
◆ MAR : Memory Address
Register

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 10


Instructions of CPU
◆ There are 4 types of instructions:

1. Data transfer between memory and CPU registers


2. Arithmetic and Logic Operations on data
3. Program Sequencing and Control
4. I/O transfer

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 11


Basic instruction types : three
address instruction
D = A+B+C

◆ LOAD R0,[10000]
◆ LOAD R1,[10001]
◆ ADD R2, R0, R1
◆ LOAD R0,[10002]
◆ ADD R1, R0,R2
◆ STORE [10003],R1

Note ADD R2,R0,R1 means R2 = R0+R1


240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 12
Basic instruction types : two
address instruction
D = A+B+C

◆ LOAD R0,[10000]
◆ LOAD R1,[10001] M
◆ ADD R0,R1
◆ LOAD R2,[10002]
◆ ADD R0,R2
◆ STORE [10003],R0

Note ADD R0,R1 means R0 = R0+R1


240-208 Fundamental of Computer Architecture
1 0 0 0 0
Chapter 3 - The Processing Unit 13
Basic instruction types : one
address instruction
D = A+B+C

◆ LOAD [10000]
◆ ADD [10001]
◆ ADD [10002]
◆ STORE [10003]

Note ADD [10001] means Acc = Acc + [10001]

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 14


CPU registers
◆ General purpose registers
◆ R0,R1…Rn

◆ A,B, C,….

◆ Special purpose register


◆ PC

◆ SP

◆ Accumulator

◆ Flag or Condition code

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 15


PC :Program Counter register

◆ Used to keep the next address of memory that


CPU want to access

◆ PC and address-bus have the same size

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 16


PC :Program Counter
(continued)

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 17


PC :Program Counter
(continued)

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 18


PC :Program Counter
(continued)

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 19


PC :Program Counter
(continued)

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 20


PC :Program Counter
(continued)

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 21


PC :Program Counter
(continued)

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 22


Branching
[25000] = [10000]+[10002]+[10003]+….+[24999]
LOC35000: LOAD R0,#0

LOC35003:
LOAD R1,#14999
LOAD R3,#10000
LOAD R2,[R3]
Me
ADD R0, R2
INC R3
DEC R1
Branch_NZ
LOC35003
STORE [R3],R0

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 23


Flag or Condition code
Register
◆ keep the status after perform arithmetic and logic
operation

ample: Flags of CPU z80


7
240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 24
Addressing modes of CPU
◆ Immediate #value load R0,#00001

◆ Register Ri load R0,R1

◆ Direct(absolute) [mem_loc] load R0,[100000]

◆ Register indirect [Ri] load R0,[R1]

◆ Relative X[PC]
◆ Index

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 25


Immediate addressing
◆ load R1,#00001

Bef
240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 26
Direct addressing
◆ LOAD R1,[1200H]

Be
240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 27
Register indirect
◆ load R0,[R1]

Bef
240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 28
Index addressing
◆ Use index register
◆ Effective address = X + [Ri]
◆ When X = offset (or displacement)
◆ Ri = index register or Base register

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 29


Index addressing

Offset is given as a constant


240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 30
Index addressing

Offset is in the index register


240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 31
Example1 : Transfering bytes of data

◆ Copy values in memory location 1000h-1400h to


location 2000h-2400h (1024 byte)

240-208 Fundamental of Computer Architecture


1 Chapter 3 - The Processing Unit
0
32
Example1 : Transfering bytes of data

STRT: LD R0,#1000H
LD R1,#2000H
LD R3,#1024
LOC_A: LD R4, [R0]
STORE [R1], R4
INC R0
INC R1
DEC R3
BRANCH>0 LOC_A
CALL PRINTF

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 33


Example2:
Unsigned Multiplication by Repeated Addition

◆ Multiply
8-bit unsigned number
◆C = A * B

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 34


Example2:
Unsigned Multiplication by Repeated Addition

STRT : LOAD R1,#0


LOAD R3, [mem_loc_A]
LOAD R2, [mem_loc_B]
Compare R2,#0
Branch_Z STR
LOOP: ADD R1,R3
DEC R2
Branch>0 LOOP
STR: STORE [mem_loc_C],R1

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 35


Basic processing unit
◆ the structure of simple CPU
◆ How the internal parts of CPU work
◆ How to design the simple processor
◆ Datapath

◆ Control Unit

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 36


Inside simple CPU with Single-
bus Datapath

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 37


Perform instruction ADD R1,R2
◆ MAR <= PC
◆ ADDRESS_BUS <= MAR, read
◆ MDR <= MEMORY[MAR]
◆ IR <= MDR Fetch phase
◆ Z <= PC + 4
◆ PC <= Z
◆ Y <= R1
◆ Z <= Y + R2
◆ R2 <= Z
Execution
phase

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 38


Perform instruction ADD R1,R2
Active
Signals

◆ MAR <= PC PCout, MARin


◆ ADDRESS_BUS <= MAR,read read
◆ MDR <= MEMORY[MAR] MDRinE, WMFC
◆ IR <= MDR MDRout,IRin
◆ Z <= PC + 4 PCout, MUX_sel4, Add,Zin
◆ PC <= Z Zout,PCin
◆ Y <= R1 Yin, R1out
◆ Z <= Y + R2 R2out, MUX_selY, Add, Zin
◆ R2 <= Z Zout, R2in

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 39


How to modify FETCH
operation to be faster

MAR <= PC
ADDRESS_BUS <= MAR,
Read
MDR <= MAR <= PC, Read, Z <= PC+4 , MDR <= MEMORY[MAR]
MEMORY[MAR], WMFC PC <= Z, WMFC
IR <= MDR
IR <= MDR
Z <=
PC + 4
PC <= Z

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 40


Modified FETCH operation
Active
Signals
MAR <= PC, Read, Z <= PC+4 , MDR PCout, MARin, Read, Mux_sel4,
<= MEMORY[MAR] Add, Zin
PC <= Z, WMFC Zout, PCin, Yin, WMFC
IR <= MDR MDRout, IRin

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 41


Three-bus organization
b u s A

b u s B

C o n s t a n t 4

M U X
Data bus

Instruction Decoder
Control Unit and B A

incrementer
R(n-1)
A L U
MDR

PC
R1

R0
Address bus

IR

:
MAR

. . . .

c o n t r o l s i g n a l s

b u s C

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 42


Perform Instruction ADD
R6,R5, R4

Step Action
◆ 1 PCout, R=B, MARin, Read, incPC
◆ 2 WMFC, MDRin_from_databus
◆ 3 MDRout_busB, R= B, IRin
◆ 4 R4out_busB, R5out_busA, Add, R6in,
End

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 43


Control sequence for instruction
ADD R1,(R3)
Step Action
1 PCout , MARin , Read, Select4, Add, Zin
2 Zout , PCin , Yin , WMFC
3 MDRout , IRin
4 R3out , MARin , Read
5 R1out , Yin , WMFC
6 MDRout , SelectY, Add, Zin
7 Zout , R1in , End

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 44


Control sequence for
instruction Branch
Step Action
1 PCout , MARin , Read, Select4, Add, Zin
2 Zout , PCin , Yin , WMFC
3 MDRout , IRin
4 Offset-field-of-IRout , ADD, Zin
5 Zout , PCin , End

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 45


Control sequence for
instruction Branch<0
Step Action
1 PCout , MARin , Read, Select4, Add, Zin
2 Zout , PCin , Yin , WMFC
3 MDRout , IRin
4 Offset-field-of-IRout , ADD, Zin , if N=0 then
End
5 Zout , PCin , End

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 46


Control Units
◆2 types of Control units
◆ Hardwired

◆ Microprogrammed

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 47


Hardwired Control Unit
C o n t r o l S t e p
C l o c k
C o u n t e r

E x t e r n a l I

D e c o d e r /
I R
E n c o d e r

C o n d i t i o n

C o n t r o l s i g n a l s
240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 48
Control Unit organization
C o n t r o l S t e p
C lo c k
C o u n t e r

S t e p d e c o d e r

T1
T2

Tn
I N S 1
I N S 2 E x t e r n a l I n p

I N S 3
I n s t r u c t io n
I R E n c o d e r
D e c o d e r

C o n d i t i o n c o
I N S m

R u n E n d

240-208 Fundamental of Computer Architecture C o n t r o l s ig a l s 3 - The Processing Unit 49


n Chapter
Zin and END control signals

Zin = T1 + (T6⋅ ADD) + (T4 ⋅ BR)+…..


End = (T7 ⋅ ADD) + (T5 ⋅ BR) + (((T5 ⋅ N)+(T4
⋅ N)) ⋅ BRN)+....
Note
BR = Branch instruction
BRN = Branch<0 instruction
N = Negative flag

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 50


Generation of Zin control
signal
T 6

A d d
T 4 Z i n

B R

T 1

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 51


Generation of END control
signal
T 5
B R

N
E n d
B R N

T 4
A d d
T 7

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 52


Microprogrammed control
unit E x t e r n a l
in p u t s
S t a
r t in g a n d
I R b r a n c h a d d r e s Cs o n d i t i o n
g e n e r a t o r c o d e s

C lo c k u P C

C o n t r o l s t o r e C o n t r o l W

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 53


“Control words” stored in
“Control Store”

From Figure 7.15 page 430 of “Computer Organization”, 5th


edition, Carl Hamacher, McGraw Hill

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 54


Thank you

240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 55

You might also like