Low Power CMOS Digital Design

Q:-1 What is summary of this paper?

Ans: Low power need optimization at all level.

Sources oof power dessipation are well charactrized.

Power dissipation is beecoming prime design constrain.

This research paper introduces us to low power CMOS design. This

 In this discussion they became clear that the dominant component of power
consumption in CMOS circuit from the dynamic charging and discharging of
capacitance with the power consumption. Reducing of power can be achieved by
reducing the physical capacitance.
 Techniques were presented for reduction of these various factors and these
techniques tended to follow certain recurring themes such as trading area and
performance of power & avoid waste. Trading performance for power turned out
to be a particularly important strategies and plans.
 The algorithem that is being implemented may be sequential in nature and have
feedback which will limit the degree of parallel that can be exploited.
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 Another possibility is that the optimum degree of parallelism may be so large that
the number of transistor may be inordinately large it will make the optimum
solution unreasonable. However, our goal is minimizing power consumption.
Q:-2 What are problems discussed in this paper?
 1 CMOS
 Complementary metal oxide semiconductor is a techhnology for construction od
intregrated circuits. Uses of CMOS technology are
 Microprocessor
 Microcontrllers
 Static RAM
 2 Digital electronic
 Digital electronics or digital circuits that handle digital signal rather then continous
range
 1 Dynamic power consuption
 2 power consumption
 3 short circuit current
 Short circuts are the paths b/w supply rails during switching
 Leakage
 Q3:-what method use to reduse power in CMOS Digital Design?
 There are many power technique , how ever some are here
 Clock Gating
 Power gating
 Variable frequency
 variable device threshold
 Minmize usage of low VT cells
 Back baising
 Q:-4 What solution purposed in this research?
 ANS: There are following solutions:
 Clock Gating
 Power gating
 Variable frequency
 Variable device threshold
 Q5:- What should we do to make it more better?
 Power dissipation is become one of the most signifcant parametrs in very large
scale intgration design due to trend toward portable computing and
communication system. Voltage scalling with multiple supply voltage is very tough
and challenging problems since the size of its solution space is n(l)where l is
number of supply voltage and n is number of gate.
• Q6:-
• Write conclusion ?
 There are many steps that shoulld taken which include the style of logic ,the
technology used and logic implemented.
 Factors that were shown to contribute to power dissipation include spurious
transition due to hazard and critical and race condtion , leakage and dierect path
current pre charge transition and power consuming transition
 A pass gate logic family with modified threshold voltage found to be the best
performance for CMOS due to minimal number of transistors required to
implement the importnt function
 Limition which may not allowd the optimum supply voltage are to be achived .
 Optimum degree of parallesim may be so large that the number of transistors may
be inordinatly large ,thus making the optimum solution unreasonable. however in
any case the goal in minimizing the power is clear. Operate the circuit as slowly as
possible with the highest possible supply.
 Minimum sized transistors should be used if the parastick capacitance are less
then the active gate capacitances in cascade of logic gate
 Assignment
 DLD
• Submitted by
• QaZal iftikhar
• Submitted to
• Teacher Yasir
• Student ID
• “47”