The Applications of Nano Materials

The Applications of
Nano Materials
Department of Chemical and
Materials Engineering
San Jose State University
Zhen Guo, Ph. D.

How to study Nanomaterials
Part I -- Done
Basic Materials Science Principles
Materials Processing Microstructure Properties Applications
Part II – Done Part III – This one
Instructor: Dr. Zhen Guo

Session 10, Slide 2
MatE 297, Spring 2006
The Applications of Nano Materials
Electronics Magnetic
Structure Device
Daily Life
Nano Materials Optics
consumable Applications
Renewable
Energy
MEMS
Bio Device

Session 10, Slide 3
Applications of Nano Materials
Week 9 Application (I) – Nano grained structural Quiz #4
03/22 materials and Nano Composite 1st Draft Due (3 copies)
Week 10 Application (II) – Nano Electric Materials: Blue Sheet #4
04/06 Quantum Computing Logic Device and Peer review comment Due
memory
Week 11 Application (III) – Nano Materials and Prof. David Mitlin
04/13 Renewable Energy source University of Alberta
Week 12 Application (IV) – Nano Magnetic Prof. Jiangyu Li
04/20 Materials University of Washington
Week 13 Application (V) – Nano materials Dr. Geetha Dholakia
04/27 applications on Aerospace NASA AMES Research Center
Week 14 Applications (VI) -- Biochemical Properties Dr. Sun Lei

05/04 of Nano Materials Digital Health, Intel Corp.
Week 15 Application (VII) – Nano Materials and Dr. Danielle Chamberlin,
05/11 Optical Device Agilent Corp
(Term paper due)

Session 10, Slide 4
Session X – Nano Electric Materials
-- Single Electron Transistor

-- Other Novel Transistor
-- Nano Crystal Memory
-- Phase Change Memory

Session 10, Slide 5
MOSFET Principles
• Review MOSFET principles – accumulations, depletion, and

inversion. Vt, Vg, Ids, Idsat, etc.
• Just remember that Electrons are like water, source / drain
like two bottles, channel is a pipe in between and gate is like
a valve to open / close the pipe...
Session 10, Slide 6
Single Electron Box
Single Electron Box
 One Quantum Dot
 Two Electrodes
 Tunneling Junction
 Control Gate Capacitor
Electrons are injected/ejected
into / from quantum dots thru
tunneling junctions.
Extra electrons injected into
quantum dots will lead to
excessive charging energy Courtesy from Rainer Waser: Nano-
electronics and Information technology
Instructor: Dr. Zhen Guo PP427-445
Session 10, Slide 7
Coulomb Blockade
Coulomb Blockade is caused by excessive charging energy Wc
which increase as the size of quantum dot decrease
With adding extra electron into QD
Q r => Csp => Wc
Wc=e /2Csp
2 V  Csp  4 0 r
4 0r
When Wc >> kT, thermal energy is no longer sufficient to
overcome excessive charging energy => Coulomb Blockade
Quantum Effect of Coulomb Blockade – Quantum confinement
cause energy level split => next electrons may need to occupy
higher energy level
Wc = e2/2Csp + E (n)
http://www.plus2physics.com/capacitors/study_material.asp
Session 10, Slide 8
Bias Condition for Coulomb Blockade
When gate voltage is zero, the charge at quantum dot is zero.
As gate voltage increases to a certain value, electrons are
attracted to quantum dot, making 1e net charge of dot
Further increase gate voltage will increase electron number.
Q 2
Qg2 e 2n 2  Ct CgVg2
Wc ( n )  
t

2Ct 2Cg 2(Ct  C g )
enC gVg  Ct C gVg2
F ( n )  Wc ( n )  A( n ) A(n )  Vg Qg 
(Ct  C g )
Qt  Qg   ne
e 2 n 2  2enC gVg  Ct CgVg2
Qt Qg
  Vg
F (n ) 
Ct Cg 2(Ct  Cg )

Session 10, Slide 9
Bias Condition for Coulomb Blockade
To maintain the electron number in quantum dots, we have
F ( n )  F ( n  1)
To substitute the equations in previous slide, we obtained
e 2n 2  2enCgVg  Ct CgVg2 e 2 ( n  1)2  2e(Cn  1)C V  C C V 2
F (n)   F ( n  1)  sp 4 r

0
g g t g g
2(Ct  C g ) 2(Ct  C g )
e 2n 2  2enCgVg  e 2 (n  1)2  2e( n  1)C gVg
1 e
2eC gVg  e (2n  1)  Vg  (n  )
2
2 Cg
When Consider both sides, we have
1 e 1 e e Ct
(n  )  Vg  ( n  ) or Qt  Qc 
2 Cg 2 Cg 2 Ct  Cg
Courtesy from Rainer Waser: Nano-electronics and Information technology

Session 10, Slide 10
Single Electron Transistor (SET)
SET – three terminal switching device that can
transfer electron one by one from source to drain
-- can be considered
as two independent
tunneling junctions
-- Each will have to
satisfy Coulomb 1 e C V  CdVd 1 e
Blockade conditions (n  )
2 C g  Cd
 g g
C g  Cd
 (n  )
2 Cg  Cd
1 e 1 e
(n  )  Vg  (n  )
2 Cg 2 Cg
Courtesy from Rainer

Waser: Nano-electronics and
Information technology 1
(n  )
e

C gVg 1
 Vd  ( n  )
e
2 Cg  Cs C g  Cs 2 C g  Cs

Single Electron Transistor (SET)
Con’d: Two Equations can be reduced to
1 e 1 e
( ne   CgVg )  Vd  ( ne   C gVg ) Source
Cd 2 Cd 2 Blue Line
e e
C gVg  ne  C gVg  ne  Drain
2 V  2
C g  Cs
d
C g  Cs
Red Line
• In grey area, both source and drain satisfy coulomb

blockade condition for same n value=>Fixed #
electrons.
• In green area, source and drain satisfy different value.
-- In Area A, for source junction, it satisfy n=1 so one
electron will tunnel from source to QD
-- Once electron at QD, it found that drain junction is
favor n=0 so this electron will further tunnel to drain
-- Current Flow from source to drain
-- Giving a small Vds, Ids will vary with Vg periodically
-- Vg can behave as a switch. Vg=0, need Vds greater
than threshold, Vg=e/2Cg, linear Ids verse Vds
Fabrication of SET (I)
• PADOX – Pattern Dependent Oxidization
-- 1-D Si Nano Wire connected with 2-D Si layers at both ends
-- Oxidization process forms tunneling barriers at both ends.
-- Can be either width or thickness modulated.
-- For Vertical PADOX, it is possible to form 2 tiny islands

Fabrication of SET (II)
• Surface-Treated SOI Channel
-- 1-D SOI channel intentionally undulated with alkaline based solutions
-- The nano scaled undulation results in potential fluctuation due to the
difference of quantum confinement effect from one part to another.
-- The channel effectively splits into several quantum dots.
-- Process is completely compatible with current CMOS fabrications

Advantage and Disadvantages
Advantages:
 Lower power assumption
 Good scalability
Disadvantages
 Operated usually at low temperature
 High output impedance due to tunneling
 Vds has to be less than Vg to have gate fully
control the switch.

Other Novel Logic Transistor
Ferro-Electric Field Effect Transistor (FeFET)
-- On state: for positive gate
voltage, the polarization vector
P is directed towards Channel.
-- Cohesive voltage Vc keep
remanent polarization Pr large
enough to invert channel and
keep current flow even when
Vg=0 (non-volatile operation)
-- Off State: negative gate
voltage will bring Pr direct
opposite to channel and +
charge are accumulated in the
channel region. Channel
resistance is high and no
current flow
Courtesy from Rainer Waser: Nano-electronics and Information technology
Spintronic transistor – based on the effect of spin
orientation on electron’s transportation properties
-- Source and drain are both ferro-
magnetic materials with identical
magnetization direction
-- Channel is a hetero-junction of
semiconductor compound with a highly
mobile 2-D electron gas.
-- Source will inject a spin-polarized
current into channel. Without gate
voltage, spin will remain unchanged so
electron travel to drain on a very high
velocity (1% of speed of light)
-- When applied gate voltage, spin
direction will be rotated by magnetic field
so the spin is no longer aligned with
drain side => More scattering, higher
resistance, lower velocity.
Molecular transistor – Single Molecular acting
as electronic switch and storage elements

Nano Crystal Memory
Introduction
Why Nano Crystal Memory
New Development on Nano Crystal Memory
Traditional Floating Gate Memory Nano Crystal Flash Memory
Floating Gate
Usually Poly Si

Recent Trend in Non-volatile Memory
• Current flash memory is continuing to follow
Moore’s Law at 90 / 65 / 45nm Nodes
-- 18 years for 9 generations
• ETOX and NAND will still be the mainstream

flash memory in next 5 years.
• There is no clear roadmap to continuously

scale flash memory beyond 32nm node.

ITRS Roadmap for Emerging Memory Device (2003)
63

Nano-crystal Memory for
Technology Gap
S. J. Baik et al, IDEM, 2003

Principle of Nano Crystal Memory
Traditional Floating Gate Memory Nano Crystal Flash Memory
Floating Gate
Usually Poly Si
Improvement of Data Retention and SILT.

Nano Crystal as Storing Bit
Nano Crystal Technology has been studied
extensively to replace traditional floating gate as
charge storage media.
Advantages:
 Scalability with Channel Tunneling and Erase
 Compatible with Traditional CMOS Platform
 Improved Charge Retention and Endurance
 Potential Multi Bit usage
Challenges:
 Strictly control the size and distribution of nano crystals
 Still Litho node limited
 Much work to be done for a integrated reliable and high
yield process
Silicon Nano Crystal as Storing Media
• Reduce SILC and thus

improve data retention and
endurance
• Decrease gate coupling
and thus improve leakage
and erase saturation
• Possible multi-bit storage
as particle size goes down
to discrete energy state of
electrons
R. Muralidhar et al. IDEM, 2003
Metal Dots as Storage Media
C. Lee, et al, IDEM, 2003

• Metal dots can be Co, W or Au
• Suppose to be better than Si as
work function is higher (more
attractive to electrons)
• Multilayer can improve retention
and endurance
M. Takata, et al, IDEM, 2003
Silicon Nano Crystals Produced by
CVD Methods (I)
• A Si-rich SiOx thin film is
deposited on Si surface by
PECVD method. The non-
stoichemetry are controlled by
gas flow ratios.
• An furnace annealing were

performed on this film at
1000C in N2 atmosphere to
precipitate Si Nano crystals
out of supersaturated film.
-- U.S. Pattern Pending
Si – SiO2 Binary Phase Diagram
-- Si has no solubility in SiO2 at equilibrium state

Silicon Nano Crystals Produced by
CVD Methods (II)
• Thermal Decomposition of
SiH4 precursor on Silicon
surface for Si Nano crystals .
• No Anneal Step is required.
• Most compatible with current

CMOS technology.
• Challenge is how to control

location and size distribution.
-- U.S. Pattern Pending
Other Ideas of Synthesis Nano Crystals
Controllable Nucleation and Growth

Volmer-Weber Growth (3-D Island
Growth) on Thin Film
In-Situ Phase Segregation (Spinodal
Decomposition)
Pre-patterned Growth (Polymer Precursor
Self-assembly)

Summary
Nano storing bit can and must meet Si
technology in 5 years.
Nano crystal memory is the most promising
one to be compatible with CMOS platform
Many challenges still exist ranging from
manufacturing nano particles to integration
into traditional process flow
Materials scientist can definitely help!

Phase Transformation Memory
• Same principle as DVD Phase Transformation Memory
• Using transformation
between amorphous and
crystalline phase based
on cooling speed.
• Different phases has
different optical and
electrical properties.
• Easy to be integrated
and scalable.

Stephen Lai, Intel, December 2003.
Basic Architecture of Nano Crystal Memory
R. Muralidhar et al. IDEM, 2003 S. Tiwari et al. Appl, Phy lett, 1996
Floating nano crystals can be

-- Silicon nano crystals (multiple or single)
-- Silicon nano wires
-- Metal nano dots (single
Instructor: Dr. Zhenor Multi layers)
Guo
Nucleation and Growth Control
• Nano particles need strong
nucleation and slow growth
• Low temperature (high T)
promote nucleation and
slow down growth
• The distance among
nucleation sites has to be
bigger than diffusion length
• Nucleus size should be
controlled around critical
radius
Volmer-Weber Growth
• 3-D island growth
• Neither complete wetting

nor complete non-wetting
surface
• Island size and distribution

controlled by heterogeneous
nucleation sites
 f  s   i   f  s
Spinodal Decomposition
Spontaneous transformation
due to instability
No nucleation barriers-only
require local compositional
fluctuations
Wave length (or particle size)
is a function of undercooling
Misfit strain will also play a
key role in particle size
(barriers for growth)

Self-Assembly Patterning
K. W. Guarini et. al. IDEM, 2003


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The Applications of

Zhen Guo, Ph. D.

Materials Processing Microstructure Properties Applications

Part II – Done Part III – This one

Instructor: Dr. Zhen Guo

Instructor: Dr. Zhen Guo

Week 14 Applications (VI) -- Biochemical Properties Dr. Sun Lei

Instructor: Dr. Zhen Guo

-- Single Electron Transistor

Instructor: Dr. Zhen Guo

• Review MOSFET principles – accumulations, depletion, and

Instructor: Dr. Zhen Guo

F (n)   F ( n  1)  sp 4 r

Courtesy from Rainer Waser: Nano-electronics and Information technology

Courtesy from Rainer

Instructor: Dr. Zhen Guo

• In grey area, both source and drain satisfy coulomb

Instructor: Dr. Zhen Guo

Instructor: Dr. Zhen Guo

Instructor: Dr. Zhen Guo

Instructor: Dr. Zhen Guo

Instructor: Dr. Zhen Guo

• ETOX and NAND will still be the mainstream

• There is no clear roadmap to continuously

Instructor: Dr. Zhen Guo

Instructor: Dr. Zhen Guo

S. J. Baik et al, IDEM, 2003

Traditional Floating Gate Memory Nano Crystal Flash Memory

Improvement of Data Retention and SILT.

Instructor: Dr. Zhen Guo

• Reduce SILC and thus

C. Lee, et al, IDEM, 2003

• An furnace annealing were

Instructor: Dr. Zhen Guo

• No Anneal Step is required.

• Most compatible with current

• Challenge is how to control

Controllable Nucleation and Growth

Instructor: Dr. Zhen Guo

Instructor: Dr. Zhen Guo

Instructor: Dr. Zhen Guo

Floating nano crystals can be

• Neither complete wetting

• Island size and distribution

Instructor: Dr. Zhen Guo

K. W. Guarini et. al. IDEM, 2003

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