These slides incorporate figures from Digital Design

Principles and Practices, third edition, by John F.

Wakerly, Copyright 2000, and are used by permission.
NO permission is given to re-use or publish these
figures, in either original or modified form, in printed,
electronic or any other format.
 Slide Set 9

Latches
Flip-flops
Sequential PLAs
 Sequential Circuits
• Output depends on current input and past
history of inputs.
• “State” embodies all the information about the
past needed to predict current output based
on current input.
– State variables, one or more information bits.
 Describing Sequential Circuits
• State table
– For each current-state, specify next-states as
function of inputs
– For each current-state, specify outputs as function of
inputs
– Like a separate combinational problem for each state
• State diagram
– Graphical version of state table

1/1
0/0

0/0 q0 q1

1/1
 Clock signals
• Very important with most sequential circuits
– State variables change state at clock edge.
 Bistable element
HIGH LOW

LOW HIGH

LOW HIGH

HIGH LOW
 Analog analysis
• Assume pure CMOS thresholds, 5V rail
• Theoretical threshold center is 2.5 V
 Analog analysis
• Assume pure CMOS thresholds, 5V rail
• Theoretical threshold center is 2.5 V

2.51
2.5
4.8 V
5.0 VV 2.5 V
2.0
0.0

2.5 V
2.0
0.0 2.5
4.8 V
5.0 V
 Metastability
• Metastability is inherent in any bistable circuit

• Two stable points, one metastable point

Another look at metastability
Why all the harping on metastability?
• All real systems are subject to it
– Problems are caused by “asynchronous inputs”
that do not meet flip-flop setup and hold times.
• Especially severe in high-speed systems
– since clock periods are so short, “metastability
resolution time” can be longer than one clock
period.
• Many digital designers, products, and
companies have been burned by this
phenomenon.
Back to the bistable element
• cross-coupled inverter maintains a zero or one,
but has no provision for forcing a change
• enter the set-reset (S-R) latch
• cross-coupled NOR gates

(control = 0) ==> inverter

(control = 1) ==> zero out
S-R latch operation

Metastability is possible
if S and R are negated
simultaneously.
 S-R latch timing parameters
• Propagation delay
• Minimum pulse width
S-R latch symbols
S-R latch using NAND gates
also called S R latch

(control = 1) ==> inverter

(control = 0) ==> one output

Differs from NOR implementation:

controls are active-low
set control drives Q gate
S-R latch with enable
D latch
 D-latch operation

latch acts like a wire while its control is active

flip-flop (later) grabs data when control changes
 D-latch timing parameters
• Propagation delay (from C or D)
• Setup time (D before C edge)
• Hold time (D after C edge)
 Construct edge-triggered D flip-flop
• two D latches in series
• driven by opposite clock phases
• first stage is the master
• second stage is the slave
• master-slave D flip-flop

note edge-trigger
clock symbol
Edge-triggered D flip-flop behavior
 D flip-flop timing parameters
• Propagation delay (from CLK)
• Setup time (D before CLK)
• Hold time (D after CLK)
Edge-triggered D flip-flop with
asynchronous preset and clear

master slave
• release during low clock ==> slave reverts to cross-coupled inverters, master tracks D
• release during high clock ==> master reverts to cross-coupled inverters, slave tracks master (stable 1)
• release during low-to-high at slave ==> slave captures master, which is already cross-coupled inverters
• release during low-to-high at master ==> master captures D, but slave isolates with stable one

tracks clock', but no further effect

assert preset forces one

tracks D' when clock is low
one when clock is high, but no further effect

1
1

1
1 0
0

circuit exhibits pattern above, regardless of data and clock,

assuming clear remains unasserted
 TTL edge-triggered D circuit
• Preset and
clear inputs
– like S-R latch
• 3 feedback
loops
– interesting
analysis
 reverts to 1 (captured D = 1)
tracking D 0 (captured D = 0)

so, captured D’ also stable

sets
Q=D
stable
1
D’

01

01 1
D

in either case
captured D is stable

tracks D’ (captured D = 1)
trackingor
D’
reverts to 1 (captured D = 0)
Variant: edge-triggered D flip-flop
--- multiplexes input D or output Q to flip-flop
 CMOS edge-triggered D circuit
• Two feedback loops (master and slave latches)
• Uses transmission gates in feedback loops
 Other D flip-flop variations
• Negative-edge triggered

• Clock enable

• Scan
 Scan flip-flops -- for testing

• TE = 0 ==> normal operation

• TE = 1 ==> test operation
– All of the flip-flops are hooked together in a daisy
chain from external test input TI.
– Load up (“scan in”) a test pattern, do one normal
operation, shift out (“scan out”) result on TO.
J-K flip-flops
 SR master-slave

note pulse catching

S has positive glitch (of sufficient duration) during high clock ==>
master sets ==> slave sets on falling clock transition
SR master-slave timing
 JK master-slave

note pulse catching still a problem

if Q is zero, positive glitch on J during high clock sets master
slave follows after clock goes low
JK master-slave timing
Edge-triggered JK flip-flop
removes pulse catching
Commercial edge-triggered JK flip-flop
similar to edge-triggered D flip-flop
Analysis: as before
--- NAND requires all ones on inputs to achieve zero out
--- NOR requires all zeros on inputs to achieve one out
transitions to zero for: two input ones
set, toggle a zero, hold a one acts like inverter for remaining input
(i.e., set Q)

tracking: 1 if set (J = 1, K = 0)
0 if reset (J = 0, K = 1)
Q’ if toggle (J = 1, K = 1)
Q if hold (J = 0, K = 0) stable output
1

0
1

0
1 1

transitions to zero for:

JQ’ reset, toggle a one, hold a zero
J’K + J’Q’ + KQ
(i.e., reset Q)
K’Q

tracking: 0 if set (J = 1, K = 0) two input ones

acts like inverter for remaining input
1 if reset (J = 0, K = 1)
Q if toggle (J = 1, K = 1)
Q’ if hold (J = 0, K = 0)
 Suppose this signal transitions to zero

forces stable zero

while clock is high,
independent of input
transitions to one changes to J, K
no longer tracking
J, K inputs
1 stable output
0

0
1

0
1 1

stable zero now forces stable one

here while clock is high, regardless
JQ’ of inputs J, K
J’K + J’Q’ + KQ

K’Q
 T flip-flops
• Important for counters
Sequential
PALs
• 16R8
 One output of 16R8

• 8 product terms to D input of flip-flop

– positive edge triggered, common clock for all
• Q output is fed back into AND array
– needed for state machines and other applications
• Common 3-state enable for all output pins
 PAL16R6
• Six registered
outputs
• Two
combinational
outputs (like
the 16L8’s)
 GAL16V8
• Finally got it right
• Each output is
programmable as
combinational or
registered
(diagram shows
only
registered outputs)
• Also has
programmable
output polarity
GAL16V8 output logic macrocell
 GAL22V10
• More inputs
• More product terms
• More flexibility
GAL22V10 output logic macrocell
Sequential PLD timing parameters

First PLD feeding a second

with same clock
output from first must arrive at
second at least setup time before clock edge
==> stable output time plus setup time must
not exceed a clock period