Organizing Engineering

Research Papers (15)

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Wireless sensor networks (WSNs) have been extensively
studied owing to the potential applications such as in military
surveillance, elderly health care and house security. WSN devices
largely operate under resource-limited conditions. Computing
capability, energy, and communication bandwidth are the most
precious resources.
However, a secure and energy-aware communication
protocol on WSN is still unavailable for practical applications.
Although the S-MAC protocol developed by We Ye et
al. presents an example of specific research interests, the protocol
addresses only energy conservation and self-configuration-related
issues.
Applying the S-MAC protocol to conjugate with other
security protocols increases the connection delay of WSN by roughly
30-50%, making it impossible to establish a reliable and efficient WSN.
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Based on the above, we should develop a novel
security protocol, capable of cooperating efficiently with other
energy-conserving communication protocols.
To do so, a complex WSN can be constructed
to function as the operating platform. Next, the performance of
three communication protocols can be evaluated when operating
with several security protocols, including the proposed one.
Moreover, the drained energy and timing cost can be compared
statistically to yield the simulation results.
As anticipated, the power consumption does not
increase, and the overhead on connection delay is under 20%.
Importantly, the proposed protocol can be adopted
to establish the foundation of energy-efficient and dependable
WSNs.
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Time-to-market delivery in semiconductor manufacturing is of
priority concern in advanced R&D technology development. Ensuring
that products reach time-to-market delivery goals requires that
operational managers and fabrication (fab) personnel fully support R&D
experimental lots (R&D Lot). Nevertheless, capacity shortage in a wafer
fab fails to comply with output requirements of customers, leading to
delays in the R&D lot schedule and the overall project.
Although an output-driven fab normally adopts Move and
Turn Rates as key performance indicators (KPI), such indicators fail to
assess the actual performance of R&D lots in monitoring R&D
experiments and ensuring (exact OR prompt) experimental delivery.
Fab managers are also interested in the overall R&D cycle time instead
of local move (NOTE: movement?) and turn rate indices, subsequently
creating a conflict among indices between R&D and fab operations.
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For instance, the error rate exceeds 25%
when using the conventional method of T/R or Cycle time
per mask layer (days). Although managers are also
concerned with solutions, the long cycle time of a R&D lot
creates vague responsibilities the wafer fab and R&D,
necessitating the development of a feasible cycle time
model.
As for the total cycle time of a R&D Lot,
TCTRD, consists of fab-run RD lot time (TCTFab) and R&D
development handling time (HT_RD). Restated, TCTRD=
TCTFab + HT_RD. Vague responsibilities and inadequate
indices may delay the lot schedule and impede time-to-
market delivery of advanced technology products.
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Based on the above, in addition to constructing an effective
performance index, we should develop an optimal R&D Lot cycle time
reduction model capable of executing timely, effective and clearly
defined measures to achieve project cycle time, regardless of whether
in R&D or in a wafer fab.
To do so, X-factors can be modified to determine the
R&D cycle time and derive the F-factor. Based on the two factors, a
model can then be constructed to shorten technology development time,
and continuously improve quality control by using the SPC chart as a
monitoring mechanism. Next, the X-factor (XFab), excluding R&D
handling time (HT_RD), can be used to determine the on-time delivery
performance of a wafer fab for an advanced R&D technology.
Additionally, the F-factor can be used to monitor the maturation process
of advanced R&D technology manufacturing and reduce lot inventory
costs.
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As anticipated, the proposed performance
indices can be used to accurately forecast the R&D lot
schedule, shorten lot cycle time and ensure time-to-market
delivery of advanced technology products. KPI design
provides global optimization benefits that link R&D and the
wafer fab.
The proposed performance index can
ultimately shorten R&D cycle time and enhance the on-time
delivery of advanced technology products by fab-run R&D
Lots. Given R&D technology trends to enhance product
quality and manufacturing maturity through KPI design,
enterprises can exploit these factors to upgrade operational
performance in semiconductor manufacturing.
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