Digital Logic and Electronic Circuits

Digital and Electronic Circuits for
Computer Systems
Lecture 0
MSIT 123 Computer Architecture and Operating Systems
Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
Signals, Logic Operators, and Gates
Name NOT AND OR XOR

Graphical
symbol
Operator x _ xy x y xy
sign and
alternat e(s) x or x x y xy x  y
Output Both inputs At least one Inputs are

Input is 0
is 1 iff: are 1s input is 1 not equal
Arithmetic 1x x y or xy x  y  xy x  y 2xy

expression
Some basic elements of digital logic circuits, with operator signs

used in this book highlighted.
University Press.
Variations in Gate Symbols
AND OR NAND NOR XNOR
Gates with more than two inputs and/or with inverted

signals at input or output.
University Press.
Gates as Control Elements
Enable/Pass signal Enable/Pass signal
e e
Data out Data in
Data in Data out
x or 0 x
x x or “high impedance”
(a) AND gate for controlled trans fer (b) Tristate buffer
e e
0 0 0
No data
1 1
x ex x or x
(c) Model for AND switch. (d) Model for tristate buffer.
An AND gate and a tristate buffer act as controlled switches or valves.

An inverting buffer is logically the same as a NOT gate.
University Press.
Wired OR and Bus Connections
ex ex
x
x
ey
ey Data out
y (x, y, z,
y Data out
or high
(x, y, z, or 0)
impedance)
ez
ez
z
z
(a) Wired OR of product terms (b) Wired OR of t ristate outputs
Wired OR allows tying together of several controlled signals.
University Press.
Control/Data Signals and Signal Bundles
Enable Compl
8
/
/ / /
/ 8 / 32 / k
8 32 k
(a) 8 NOR gates (b) 32 AND gat es (c) k XOR gat es
Arrays of logic gates represented by a single gate symbol.
University Press.
Boolean Functions and Expressions
Ways of specifying a logic function
 Truth table: 2n row, “don’t-care” in input or output
 Logic expression: w  (x  y  z), product-of-sums,

sum-of-products, equivalent expressions
 Word statement: Alarm will sound if the door

is opened while the security system is engaged,
or when the smoke detector is triggered
 Logic circuit diagram: Synthesis vs analysis
University Press.
Manipulating Logic Expressions
Laws (basic identities) of Boolean algebra.
Name of law OR version AND version

Identity x0=x x1=x
One/Zero x1=1 x0=0
Idempotent xx= x xx=x
Inverse x x  = 1 xx=0
Commutative xy=yx xy=yx
Associative (x  y)  z = x  (y  z) (x y) z = x (y z)
Distributive x  (y z) = (x  y) (x  z) x (y  z) = (x y)  (x z)
DeMorgan’s (x  y) = x y  (x y) = x   y 
University Press.
Proving the Equivalence of Logic Expressions
Example 1.1
 Truth-table method: Exhaustive verification
 Arithmetic substitution
x  y = x + y  xy
x  y = x + y  2xy
 Case analysis: two cases, x = 0 or x = 1
 Logic expression manipulation
University Press.
Designing Gate Networks
 AND-OR, NAND-NAND, OR-AND, NOR-NOR
 Logic optimization: cost, speed, power dissipation
x x x
y y y
y y y
z z z
z z z
x x x
(a) A ND-OR circuit (b) Int ermediate circuit (c) NA ND-NA ND equivalent
A two-level AND-OR circuit and two equivalent circuits.
University Press.
BCD-to-Seven-Segment Decoder
Example 1.2
e0 0
Signals to
4-bit input in [0, 9]
enable or
x3 x2 x1 x0 turn on the e5 5 1
segments
e6 6
e4 4 2
e3 3
e2
e1
The logic circuit that generates the enable signal for the lowermost
segment (number 3) in a seven-segment display unit.
University Press.
Useful Combinational Parts
 High-level building blocks
 Much like prefab parts used in building a house
 Arithmetic components will be covered in Part III

(adders, multipliers, ALUs)
 Here we cover three useful parts:

multiplexers, decoders/demultiplexers, encoders
University Press.
x0
Multiplexers
0 x0 0
z x0 z z
x1
x1 1 x1 1
y
y
y (a) 2-to-1 mux (b) Switch view (c) Mux symbol
e (Enable) x0 0
x0 0
/
x1 1 0
0 x1 1 z z
32 /
y0
x2 2
/ 1 32 x2 0 1
x3 3
32
y y1
x3 1
y1y0 y0
(d) Mux array (e) 4-to-1 mux with enable (e) 4-to-1 mux design
Multiplexer (mux), or selector, allows one of several inputs to be
selected and routed to output depending on the binary value of a set of
selection or address signals provided to it.
University Press.
Decoders/Demultiplexers
y1 y0
y1 y0
y1 y0
x0
0 x0
0 x0
1 x1
x1 1 x1 e
2 x2
2 x2 (Enable)
3 x3
x2 3 x3
x3
(c) Demultiplexer, or
(a) 2-to-4 decoder (b) Decoder symbol decoder wit h “enable”
A decoder allows the selection of one of 2a options using an a-bit

address as input. A demultiplexer (demux) is a decoder that only
selects an output if its enable signal is asserted.
University Press.
Encoders
x0
x1
x0 0
x1 1
x2
x2 2
x3 3
x3
y1y0
y1y0
(a) 4-to-2 encoder (b) Enc oder symbol
A 2a-to-a encoder outputs an a-bit binary number equal to the

index of the single 1 among its 2a inputs.
University Press.
Programmable Combinational Parts
A programmable combinational part can do the job of
many gates or gate networks
Programmed by cutting existing connections (fuses)

or establishing new connections (antifuses)
 Programmable ROM (PROM)
 Programmable array logic (PAL)
 Programmable logic array (PLA)
University Press.
PROMs
Inputs
w w
x x
.
Decoder
y y .
.
z z
...
Outputs
(a) Programmable (b) Logic equivalent (c) Programmable read-only
OR gates of part a memory (PROM)
Programmable connections and their use in a PROM.
University Press.
PALs and PLAs
Inputs 8-input 6-input
ANDs ANDs
...
AND OR
.
array array
(AND . (OR
plane) . plane)
... 4-input
ORs
Outputs
(a) General programmable (b) PAL: programmable (c) PLA: programmable
combinational logic AND array, fixed OR array AND and OR arrays
Programmable combinational logic: general structure and two classes

known as PAL and PLA devices. Not shown is PROM with fixed AND
array (a decoder) and programmable OR array.
University Press.
Timing and Circuit Considerations
Changes in gate/circuit output, triggered by changes in its

inputs, are not instantaneous
 Gate delay : a fraction of, to a few, nanoseconds
 Wire delay, previously negligible, is now important

(electronic signals travel about 15 cm per ns)
 Circuit simulation to verify function and timing
University Press.
Glitching
Using the PAL in Fig. 1.13b to implement f = x  y  z
x=0
a=x y
f =az
2 2
Timing diagram for a circuit that exhibits glitching.
University Press.
CMOS Transmission Gates
y
P
x0 TG
N x1
TG TG
(a) CMOS transmission gate: (b) Two-input mux built of t wo

circuit and symbol transmission gat es
A CMOS transmission gate and its use in building a 2-to-1 mux.
University Press.
Latches, Flip-Flops, and Registers
D R
R
Q Q
Q S Q
S
C
(a) SR latch (b) D latch
D D Q D Q Q D Q / D Q /
k k
FF FF
C C Q C Q Q C Q C Q
(c) Master-slave D flip-flop (d) D flip-flop symbol (e) k -bit register
Latches, flip-flops, and registers.
University Press.
Latches vs Flip-Flops
Setup Hold Setup Hold
time time time time
D latch: Q
D FF: Q
Operations of D latch and negative-edge-triggered D flip-flop.
University Press.
Reading and Modifying FFs in the Same Cycle
/ D Q /
k k
FF
C Q Computation module
(combinational logic)
/ D Q /
k k
FF
C Q
Propagation delay
Clock
Register-to-register operation with edge-triggered flip-flops.
University Press.
Finite-State Machines
Example 2.1
------- Input ------- Dime
Current S 10 S 20
Quarter
state
Reset
Dime
Reset
Reset
S 00 S 10 S 25 S 00 Dime Dime
Quarter
S 10 S 20 S 35 S 00 Start
Quarter
S 20 S 30 S 35 S 00 Quarter
S 00 S 25
S 25 S 35 S 35 S 00 Reset
S 30 S 35 S 35 S 00 Reset Dime
Quarter
S 35 S 35 S 35 S 00
Reset
Next state
S 00 is the initial state Dime
S 35 S 30
S 35 is the final state Dime
Quarter
Quarter
State table and state diagram for a vending machine coin

reception unit.
University Press.
Sequential Machine Implementation
Only for Mealy machine
Inputs Output Outputs

/ State register /
n logic m
Next-state
/
logic Next-state l
Present excitation
state signals
Hardware realization of Moore and Mealy sequential

machines.
University Press.
Designing Sequential Circuits
Example 2.3
Inputs
Quarter in q
Output Final
D Q
e state
C
FF2
Q
is 1xx
Dime in d
D Q
FF1
C Q
D Q
FF0
C Q
Hardware realization of a coin reception unit (Example 2.3).
University Press.
Shift Register
Shift
Load
Parallel data in / 0
k Parallel data out
/ D Q /
Serial data in 1 k k
FF
C Q Serial data out
k – 1 LSBs MSB
/
Register with single-bit left shift and parallel load capabilities. For
logical left shift, serial data in line is connected to 0.
University Press.
Register File and FIFO
Write 2 h k -bit registers Muxes
data / / / Write enable
D Q
k k k
Write FF Write
/ C Q / data
address h k Read
Write data 0 k/
/ addr
h
Write / D Q / Read
k k Read
enable FF data 0 / addr 0
C Q h Read
/ data 1 k/
k Read
/
Decoder
h addr 1
k
/ D Q / / Read enable
k k Read
FF
C Q data 1
(b) Graphic symbol
for register file
/ D Q /
k k
FF
C Q Push Full
/ Input Output /
h k k
Read address 0 / Read
enable Empty Pop
h
Read address 1 /
(a) Register file with random access (c) FIFO symbol
Register file with random access and FIFO.
University Press.
SRAM
Row decoder
. Square or
Write enable . almost square
. memory matrix
/ Data in
g
Data out /
g
/ Address
h
Chip Output
. . .
select enable Row buffer
. . .
Row
Address / Column mux
h Column
g bits data out
(a) SRAM block diagram (b) SRAM read mechanism
SRAM memory is simply a large, single-port register file.
University Press.
Binary Counter
Input
IncrInit
0 Mux 1
Load
0 Count register
x
c out c in
Incrementer 1
x+1
Synchronous binary counter with initialization capability.
University Press.
Programmable Sequential Parts
A programmable sequential part contain gates and

memory elements
Programmed by cutting existing connections (fuses)

or establishing new connections (antifuses)
 Programmable array logic (PAL)
 Field-programmable gate array (FPGA)
 Both types contain macrocells and interconnects
University Press.
PAL and FPGA
8-input I/O blocks
ANDs
CLB CLB
01
CLB CLB
Mu x C D
FF
Q Q
Mu x
01 Configurable Programmable
logic block connections
(a) Portion of PAL with storable output (b) Generic structure of an FPGA
Examples of programmable sequential logic.

University Press.
Binary Counter
Input
IncrInit
0 Mux 1
Load
0 Count register
x
c out c in
Incrementer 1
x+1
Synchronous binary counter with initialization capability.
University Press.
Clocks and Timing of Events
Clock is a periodic signal: clock rate = clock frequency
The inverse of clock rate is the clock period: 1 GHz  1 ns
Constraint: Clock period  tprop + tcomb + tsetup + tskew
D Q Combinational D Q
FF1 FF2
Q
logic Q
C C
Clock1 Clock2
Other inputs
Clock period
Must be wide enough

FF1 begins FF1 change to accommodate
to change observed worst-cas e delays
Determining the required length of the clock period.
University Press.
Synchronization
Asynch Synch Asynch Synch
input version input version
D Q D Q D Q
FF FF1 FF2
C Q C Q C Q
(a) Simple synchroniz er (b) Two-FF synchronizer
Clock
Asynch
input
Synch
version
(c) Input and output waveforms
Synchronizers are used to prevent timing problems arising from

untimely changes in asynchronous signals.
University Press.
Level-Sensitive Operation
D Q Combi- D Q Combi- D Q
Latch national Latch national Latch
C Q logic C Q logic C Q
1 2 1
Other inputs Other inputs

Clock period
1
Clocks with
nonoverlapping
 highs
2
Two-phase clocking with nonoverlapping clock signals.
University Press.

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Digital and Electronic Circuits for

MSIT 123 Computer Architecture and Operating Systems

Name NOT AND OR XOR

Output Both inputs At least one Inputs are

Arithmetic 1x x y or xy x  y  xy x  y 2xy

Some basic elements of digital logic circuits, with operator signs

AND OR NAND NOR XNOR

Gates with more than two inputs and/or with inverted

An AND gate and a tristate buffer act as controlled switches or valves.

(a) Wired OR of product terms (b) Wired OR of t ristate outputs

Wired OR allows tying together of several controlled signals.

Arrays of logic gates represented by a single gate symbol.

 Truth table: 2n row, “don’t-care” in input or output

 Logic expression: w  (x  y  z), product-of-sums,

 Word statement: Alarm will sound if the door

 Logic circuit diagram: Synthesis vs analysis

Name of law OR version AND version

One/Zero x1=1 x0=0

Idempotent xx= x xx=x

Inverse x x  = 1 xx=0

Commutative xy=yx xy=yx

DeMorgan’s (x  y) = x y  (x y) = x   y 

 Truth-table method: Exhaustive verification

 Case analysis: two cases, x = 0 or x = 1

 Logic expression manipulation

 Logic optimization: cost, speed, power dissipation

A two-level AND-OR circuit and two equivalent circuits.

 High-level building blocks

 Much like prefab parts used in building a house

 Arithmetic components will be covered in Part III

 Here we cover three useful parts:

A decoder allows the selection of one of 2a options using an a-bit

A 2a-to-a encoder outputs an a-bit binary number equal to the

Programmed by cutting existing connections (fuses)

 Programmable ROM (PROM)

 Programmable array logic (PAL)

 Programmable logic array (PLA)

Programmable connections and their use in a PROM.

Programmable combinational logic: general structure and two classes

Changes in gate/circuit output, triggered by changes in its

 Gate delay : a fraction of, to a few, nanoseconds

 Wire delay, previously negligible, is now important

 Circuit simulation to verify function and timing

Timing diagram for a circuit that exhibits glitching.

(a) CMOS transmission gate: (b) Two-input mux built of t wo

A CMOS transmission gate and its use in building a 2-to-1 mux.

(c) Master-slave D flip-flop (d) D flip-flop symbol (e) k -bit register

Latches, flip-flops, and registers.

Operations of D latch and negative-edge-triggered D flip-flop.

Register-to-register operation with edge-triggered flip-flops.

State table and state diagram for a vending machine coin

Only for Mealy machine

Inputs Output Outputs

Hardware realization of Moore and Mealy sequential

Hardware realization of a coin reception unit (Example 2.3).

Register file with random access and FIFO.

(a) SRAM block diagram (b) SRAM read mechanism

SRAM memory is simply a large, single-port register file.

Synchronous binary counter with initialization capability.

A programmable sequential part contain gates and

Programmed by cutting existing connections (fuses)

 Programmable array logic (PAL)

 Field-programmable gate array (FPGA)

 Both types contain macrocells and interconnects