One Day Workshop as Faculty Development Program

on
Custom VLSI Design Flow

Organized By
IETE Students Forum
ACE, Devsthali
Ambala

on
5th February, 2011

at
Electronics and Communication Engineering Department,
CONTENTS
 Introduction to MOSFET
 NMOS

 PMOS

 CMOS

Applied Research
Ambala College of Engineering and
 Inverter Cross – Section

 Fabrication

 Schematic and Layout

 Custom VLSI Design Tools (Electric and LTSpice)

 Schematic Design and Simulation

 Layout Design, DRC, LVS and Extraction

 Simulation and GDS export

2
 3: CMOS Transistor
TERMINAL VOLTAGES
Vg

Theory
 Mode of operation depends on Vg, Vd, Vs
+ +
 Vgs = Vg – Vs Vgs Vgd
- -
 Vgd = Vg – Vd Vs Vd
- +
 Vds = Vd – Vs = Vgs - Vgd Vds

 Source and drain are symmetric diffusion terminals

 By convention, source is terminal at lower voltage
 Hence Vds ≥ 0
 nMOS body is grounded. First assume source is 0 too.
 Three regions of operation
 Cutoff
 Linear
3
 Saturation
 3: CMOS Transistor
GATE CAPACITANCE

Theory
 Approximate channel as connected to source
 C = ε WL/t = C WL = C
gs ox ox ox permicronW

 Cpermicron is typically about 2 fF/µ m

polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, εox = 3.9ε0)
p-type body
4
 3: CMOS Transistor
NMOS I-V SUMMARY
W

Theory
 Shockley 1st order transistor models
β = µCox
L

 0 Vgs < Vt cutoff

  Vds V V < V
I ds =  β Vgs − Vt −  ds linear
 2 
ds dsat

 β
( Vgs − Vt )
2
 Vds > Vdsat saturation
2
5
 Fabrication and Layout
NMOS OPERATION
 Body is commonly tied to ground (0 V)
 When the gate is at a low voltage:
 P-type body is at low voltage
 Source-body and drain-body diodes are OFF
 No current flows, transistor is OFF

Source Gate Drain

Polysilicon
SiO2

0
n+ n+
S D
p bulk Si

6
 Fabrication and Layout
PMOS TRANSISTOR
 Similar, but doping and voltages reversed
 Body tied to high voltage (VDD)
 Gate low: transistor ON
 Gate high: transistor OFF
 Bubble indicates inverted behavior

Source Gate Drain

Polysilicon
SiO2

p+ p+

n bulk Si
7
 Fabrication and Layout
TRANSISTORS AS SWITCHES
 We can view MOS transistors as electrically
controlled switches
 Voltage at gate controls path from source to
g=0 g=1
drain
d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s
8
 Fabrication and Layout
CMOS INVERTER

A Y VDD
0
1

A Y

A Y
GND Slid
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 Fabrication and Layout
CMOS INVERTER

A Y VDD
0
1 0 OFF
A=1 Y=0

ON
A Y
GND Slid
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 Fabrication and Layout
CMOS INVERTER

A Y VDD
0 1
1 0 ON
A=0 Y=1

OFF
A Y
GND Slid
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 Fabrication and Layout
CMOS FABRICATION
 CMOS transistors are fabricated on silicon
wafer
 Lithography process similar to printing press

 On each step, different materials are

deposited or etched
 Easiest to understand by viewing both top
and cross-section of wafer in a simplified
manufacturing process

Slid
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 Fabrication and Layout
INVERTER CROSS-SECTION
 Typically use p-type substrate for nMOS
transistor
 Requires n-well for body of pMOS transistors
 Several alternatives: SOI, twin-tub, etc.

A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

Slid
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 Fabrication and Layout
WELL AND SUBSTRATE TAPS
 Substrate must be tied to GND and n-well to
VDD
 Metal to lightly-doped semiconductor forms
poor connection called Shottky Diode
 Use heavily doped well
A and substrate
GND V
contacts / taps Y
DD

p+ n+ n+ p+ p+ n+

n well
p substrate

substrate tap well tap Slid

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 Fabrication and Layout
INVERTER MASK SET
 Transistors and wires are defined by masks
 Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap
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 Fabrication and Layout
DETAILED MASK VIEWS
 Six masks n well

 n-well
 Polysilicon
 n+ diffusion
Polysilicon

 p+ diffusion
n+ Diffusion

 Contact
 Metal p+ Diffusion

Contact

Metal

Slid
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 Fabrication and Layout
FABRICATION STEPS
 Start with blank wafer
 Build inverter from the bottom up

 First step will be to form the n-well

 Cover wafer with protective layer of SiO2 (oxide)

 Remove layer where n-well should be built
 Implant or diffuse n dopants into exposed wafer
 Strip off SiO2

p substrate
Slid
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 Fabrication and Layout
OXIDATION
 Grow SiO2 on top of Si wafer
 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate Slid
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 Fabrication and Layout
PHOTORESIST
 Spin on photoresist
 Photoresistis a light-sensitive organic polymer
 Softens where exposed to light

Photoresist
SiO2

p substrate
Slid
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 Fabrication and Layout
LITHOGRAPHY
 Expose photoresist through n-well mask
 Strip off exposed photoresist

Photoresist
SiO2

p substrate
Slid
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 Fabrication and Layout
ETCH
 Etch oxide with hydrofluoric acid (HF)
 Seeps through skin and eats bone; nasty stuff!!!
 Only attacks oxide where resist has been
exposed

Photoresist
SiO2

p substrate
Slid
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 Fabrication and Layout
STRIP PHOTORESIST
 Strip off remaining photoresist
 Use mixture of acids called piranah etch
 Necessary so resist doesn’t melt in next step

SiO2

p substrate
Slid
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 Fabrication and Layout
N-WELL
 n-well is formed with diffusion or ion
implantation
 Diffusion
 Placewafer in furnace with arsenic gas
 Heat until As atoms diffuse into exposed Si
 Ion Implanatation
 Blast wafer with beam of As ions
 Ions blocked by SiO2, only enter exposed Si
SiO2

n well

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 Fabrication and Layout
STRIP OXIDE
 Strip off the remaining oxide using HF
 Back to bare wafer with n-well

 Subsequent steps involve similar series of

steps

n well
p substrate Slid
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 Fabrication and Layout
POLYSILICON
 Deposit very thin layer of gate oxide
< 20 Å (6-7 atomic layers)
 Chemical Vapor Deposition (CVD) of silicon
layer
 Place wafer in furnace with Silane gas (SiH4)
 Forms many small crystals called polysilicon
 Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate
Slid
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 Fabrication and Layout
POLYSILICON PATTERNING
 Use same lithography process to pattern
polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate
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 Fabrication and Layout
SELF-ALIGNED PROCESS
 Use oxide and masking to expose where n+
dopants should be diffused or implanted
 N-diffusion forms nMOS source, drain, and n-
well contact

n well
p substrate
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 Fabrication and Layout
N-DIFFUSION
 Pattern oxide and form n+ regions
 Self-aligned process where gate blocks
diffusion
 Polysilicon is better than metal for self-
aligned gates because it doesn’t melt during
later processing
n+ Diffusion

n well
p substrate
Slid
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 Fabrication and Layout
N-DIFFUSION
 Historically dopants were diffused
 Usually ion implantation today

 But regions are still called diffusion

n+ n+ n+
n well
p substrate
Slid
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 Fabrication and Layout
N-DIFFUSION
 Strip off oxide to complete patterning step

n+ n+ n+

n well
p substrate
Slid
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 Fabrication and Layout
P-DIFFUSION
 Similar set of steps form p+ diffusion regions
for pMOS source and drain and substrate
contact

p+ Diffusion

p+ n+ n+ p+ p+ n+

n well
p substrate
Slid
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 Fabrication and Layout
CONTACTS
 Now we need to wire together the devices
 Cover chip with thick field oxide

 Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+

n well
p substrate
Slid
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 Fabrication and Layout
METALLIZATION
 Sputter on aluminum over whole wafer
 Pattern to remove excess metal, leaving
wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate
Slid
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 Fabrication and Layout
LAYOUT
 Chips are specified with set of masks
 Minimum dimensions of masks determine
transistor size (and hence speed, cost, and
power)
 Feature size f = distance between source and
drain
 Set by minimum width of polysilicon
 Feature size improves 30% every 3 years or so
 Normalize for feature size when describing
design rules
 Express rules in terms of λ = f/2
 E.g. λ = 0.3 µ m in 0.6 µ m process Slid
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 Fabrication and Layout
SIMPLIFIED DESIGN RULES
 Conservative rules to get you started

Slid
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INVERTER LAYOUT

Fabrication and Layout

 Transistor dimensions specified as Width /
Length
 Minimum size is 4λ / 2λ , sometimes called 1
unit
 For 0.6 µ m process, W=1.2 µ m, L=0.6 µ m

Slid
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 Fabrication and Layout
SUMMARY
 MOS Transistors are stack of gate, oxide,
silicon
 Can be viewed as electrically controlled
switches
 Build logic gates out of switches

 Draw masks to specify layout of transistors

 Now you know everything necessary to start

designing schematics and layout for a simple
chip!
Slid
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Ambala College of Engineering and
Applied Research
38
DESIGN LAB - DEMONSTARTION