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CHAPTER 4
Introduction
BJTs amplifier requires a knowledge of both the DC analysis
(large signal) and AC analysis (small signal).
For a DC analysis a transistor is controlled by a number of
factors including the range of possible operating points.
Once the desired DC current and voltage levels have been
defined, a network must be constructed that will establish the
desired operating point.
BJT need to be operate in active region used as amplifier.
The cutoff and saturation region used as a switches.
For the BJTs to be biased in its linear or active operating
region the following must be true:
a) BE junction forward biased, 0.6 or 0.7V
b) BC junction reverse biased
Introduction
DC bias analysis assume all capacitors are open cct.
AC bias analysis :
1) Neglecting all of DC sources
2) Assume coupling capacitors are short cct. The effect of these
capacitors is to set a lower cut-off frequency for the cct.
3) Inspect the cct (replace BJTs with its small signal model).
4) Solve for voltage and current transfer function and i/o and o/p
impedances.
For transistor amplifiers the resulting DC current and voltage establish
an operating point that define the region that can be employed for
amplification process.
Slide 1 Transistor Construction
There are two types of transistors: pnp and npn-type.
The E-B junction is forward-biased and the B-C junction is reverse biased.
Robert Boylestad Copyright ©2002 by Pearson Education, Inc.
Digital Electronics Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 3 Currents in a Transistor
IE IC IB [Formula 3.1]
The base is common to both input (emitter – base) and output (collector – base) of the
transistor.
VBE=0.7V
IE=(β+1)IB≈IC
IE= IC +IB
IC = βIB
Operating Point
For transistor amplifiers the resulting dc current and voltage establish an
operating point on the characteristics that define the region that will be
employed for amplification of the applied signal.
Operating point quiescent point or Q-point
The biasing circuit can be designed to set the device operation at any of
these points or others within the active region.
The BJT device could be biased to operate outside the max limits, but the
result of such operation would be shortening of the lifetime of the device or
destruction of the device.
The chosen Q-point often depends on the intended use of the circuit.
Various operating points within the limits of operation
of a transistor
Q-point C: Q-point B:
• Concern on IC(mA) • The best operating point
nonlinearities due to I B for linear gain and largest
curves is rapidly changes possible voltage and current
PCmax is a desired condition for
in this region. • It uA
IB=60
ICmax 18 a small signal analysis
IB=50 uA
15
IB=40 uA
12
Saturation B IB=30 uA
9
6 IB=20 uA
Q-point A:
• I=0A, V=0V
• Not suitable for C IB=10 uA
3
transistor to operate
IB=0 uA
A VCE(V)
10 20 30 40
VCEsat
VCEmax
Cutoff
Fixed-Bias Circuit
For the dc analysis the network can be isolated from the
indicated ac levels by replacing the capacitors with an open-
circuit equivalent because the reactance of a capacitor for dc is
∞Ω
The dc supply Vcc can be separated into two supplies
Forward Bias of Base-Emitter
Write KVL equation in
+ the clockwise direction
VCC RB
-
C
of the loop :
IB +
B
+
VCE +VCC – IBRB – VBE =0
VBE -
E
-
+
VCE = VCC-ICRC
VCC
VCE Recall that :
-
VCE = VC – VE ; VE =ICRC
In this case, VE = 0V, so
Collector-emitter loop
VCE=VC
Example 1
Determine the following for the fixed bias configuration.
The transistor has a β= 50
c) VBE VB 0.7 V
VCE VCEQ VC 6.83 V
VCC=+16V
IC
RC=2.7kohm
RB=470kohm
C
IB +
B
VCE
+
VBE -
E
-
Solution
VCC VBE
a ) IBQ
RB
16 0.7
32.55uA
470 k
c) VBE VB 0.7 V
e) VE 0V
Slide 7 3 Regions of Operation
• Active
Operating range of the amplifier.
• Cutoff
-When IB = 0
-The amplifier is basically off. There is voltage but little
current.
- small collector leakage current
- VCE = VCC
• Saturation
- The amplifier is full on. There is little voltage but lots of
current.
- VCE SAT, base-collector junction become forward
biased and IC cannot increase no further.
- VCE SAT occur somewhere below the knee of the
collector curve.
Robert Boylestad Copyright ©2002 by Pearson Education, Inc.
Digital Electronics Upper Saddle River, New Jersey 07458
All rights reserved.
Transistor Saturation
The term saturation is applied to any system where levels have
reached their max values.
For a transistor operating in the saturation region, the current is
maximum value for a particular design.
Saturation region are normally avoided because the B-C
junction is no longer reverse-biased and the output amplified
signal will be distorted.
VCC
ICsat RC
Example 3
By refering to example 1 and the figure, determine the saturation level.
Solution
VCC 12
ICsat 5.45mA
RC 2 .2 k
Solution
VCC 16
ICsat 5.92mA
RC 2 .7 k
IC +
RC
-
+ VCC
VCE
-
Load-Line Analysis
Step 1:
Refer to circuit, VCE=VCC – ICRC (1)
Choose IC=0 mA. Subtitute into (1), we get
VCE=VCC (2) located at X axis
Step 2:
Choose VCE=0V and subtitute into (1), we get
IC=VCC/RC (3) located at Y-axis
Step 3:
Joining two points defined by (2) + (3), we get straight line that can
be drawn as Fig. 5.6.
Load-Line Analysis
IC(mA) Fig. 5.6
Load line
VCC/RC
VCE(V)
VCC
IC=0 mA
Load-Line Analysis
IC(mA)
Case 1:
VCC/RC
Q-point IBQ1
VCE(V)
VCC
Fig. 5.7:Movement of Q-point with increasing
levels of IB
Load-Line Analysis
IC(mA) Case 2:
VCC/RC1
• VCC fixed and RC change
the load line will shift as
VCC/RC2 RC3 > RC2 > RC1 shown in Fig 5.8
VCC/RC3
Q-point IBQ • IB fixed, the Q-point will
Q-point
Q-point move as shown in the same
figure.
VCE(V)
VCC
Fig. 5.8 : Effect of increasing levels of RC on the
load line and Q-point
IC(mA)
VCC1/RC
VCC2/RC
VCC3/RC
Q-point Q-point IBQ Case 3:
Q-point
• RC fixed and VCC varied,
the load line shifts as
shown in Fig. 5.9
VCE(V)
VCC3 VCC2 VCC1
Fig. 5.9: Effect of lower values of VCC on the load line and Q-point
Example 5
Given the load line of Fig. 5.10 and defined Q-point, determine the
required values of VCE, RC and RB for a fixed bias configuration.
IC(mA)
IB=60 uA
ICmax 18
IB=50 uA
15
IB=40 uA
12
IB=30 uA
9
6 IB=20 uA
Q-point IB=17 uA
IB=10 uA
3
IB=0 uA
VCE(V)
10 20 30 40
Fig. 5.10
Solution
Step 1 :
VCE VCC 40 V at IC 0 mA
VCC
IC at VCE 0V.
RC
VCC 40
RC 2.67 kohm
IC 15m
Step 2 :
VCC - VBE
IB
RB
VCC VBE
RB
IB
40 0.7
17
2311 kohm
Example 6
Determine the value of Q-point for this figure. Also find the new
value of Q-point if change to 150.
VCC=+12V
IC
RC=560ohm
RB=100kohm
C
IB +
B
VCE
+
VBE -
E
100 -
Solution
Step 1 :
100,
Thechange
The changeof of
12 - 0.7
IB
100k
113 A
ICQ & VCEQ cause
causethe the
bigchange
changeofof
IC IB 100113 11.3 mA big
Q-pointvalue.
Q-point value.
Thisshows
This shows
Step 2 : thatfixed
fixed
that
VCE VCC - ICRC biased
biased
12 - 11 .3m 560 configurationisis
configuration
5.67V Q po int 5.67 V,11 .3mA NOTstable
NOT stable
Step 4 :
VCE VCC - ICRC
12 - 16.95m 560
2.51V New Q - point (2.51 V, 16.95mA)
Emitter Bias (E-SATBILIZED BIAS)
The DC bias network below contains an emitter resistor to
improve the stability level of fixed-bias configuration.
The analysis consists of two scope:
- Examining the base-emitter loop (input loop)
- Use the result to investigate the collector-emitter loop (output
loop) VCC
IC
RC
RB
Vo
IB
Vi C2
C1
IE
Fig. 5.11 RE
Base-Emitter Loop
+
VCC RB
-
KVL : VCC - IBRB - VBE - IERE 0 (1)
IB
B known that IE 1 IB, subtitute into (1) we get,
+ VCC - IBRB - VBE - 1 IBRE 0
VBE
E Rearrange the equ, finally we get,
-
IE
VCC - VBE
IB
RE RB 1 RE
IE = IC + I B ; IC = ßIB
Base-emitter loop
IE= ßIB + IB
= (ß+1)IB
Collector-Emitter Loop
KVL : VCC - ICRC - VCE - IERE 0 (1)
Assuming IE IC rearrange equ (1) we get,
IC + VCE VCC - IC(RC RE)
RC
-
From the Fig.5.13 we also can know
C
+
VE IERE
VCC
VCE
-
VCE VC - VE
IE
RE VC VCE VE OR VC VCC - ICRC
I E = IC + I B
IC = IE
ICBO = minority collector current. This is usually so small that it can be ignored, except in
high power transistors and in high temperature environments.
ICBO
ICEO IB 0 A [Formula 3.9]
1
When IB = 0A the transistor is in cutoff, but there is some minority current flowing called
ICEO.
Robert Boylestad Copyright ©2002 by Pearson Education, Inc.
Digital Electronics Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 15 Beta ()
IC
In DC mode: dc [Formula 3.10]
IB
IC
In AC mode: ac VCE constant [Formula 3.11]
IB
Note: AC = DC
2.7mA
DC (forVCE 7.5) 108
Robert Boylestad
Digital Electronics 25A Copyright ©2002 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 17 Relationship between and
Both indicate an amplification factor.
[Formula 3.12a]
1
[Formula 3.12b]
1
[Formula 3.15]
IE ( 1)IB
IC
RC=2 kohm
RB=430kohm
IB
Beta=50
IE
b) IC IB 50 40.1 2.01mA
VCC
Solution:
VCC
ICsat
RC R E
20 20
6.67mA
2k 1k 3k
This value is about three times the level of ICQ (2.01mA =50)
for the example 7. Its indicate the parameter that been used in
example 7 can be use in analysis of emitter bias network.
Load-Line Analysis
The process to plot the load line as follows:
Step 1:
Refer to fig. 5.13, VCE=VCC – IC(RC+RE) (1)
IC +
Choose IC=0 mA. Subtitute into (1), we get RC
-
C
+ VCC
VCE
VCE=VCC (2) located at X axis -
IE
Step 2: RE
VCC
IC VCE 0V (3) located at Y axis
R C RE
Load-Line Analysis
Step 3:
Joining two points defined by (2) + (3), we get straight line that can
be drawn as Fig. 5.17:
IC
VCC/(RC+RE)
Q-point IBQ
ICQ
VCE(V)
VCEQ VCC
j) β k)α l) ICsat
VCC=+20V
30
IC
RC=2 kohm
RB=430kohm
Beta=50
IB
IE