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Logic Circuits
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Static CMOS Circuits
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Static Complementary CMOS
VDD
In1
PMOS only
In2 PUN
…
InN
F(In1,In2,…InN)
In1
In2 PDN
…
NMOS only
InN
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
NMOS Transistors
in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A B
X Y Y = X if A and B
X B Y = X if A OR B
Y
A B
X Y Y = X if A AND B = A + B
X B Y = X if A OR B = AB
Y
S D
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Complementary CMOS Logic Style
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Example Gate: NAND
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Example Gate: NOR
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Complex CMOS Gate
B
A
C
D
OUT = D + A • (B + C)
A
D
B C
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Constructing a Complex Gate
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Example: Carry Gate
C C’
F = (ab+bc+ac)’
AB 0 0 Carry ‘c’ is critical
Factor c out:
AB’ 0 1
F=(ab+c(a+b))’
A’B’ 1 1 0-cover is n-pd
1-cover is p-pu
A’B 0 1
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Example: Carry Gate (2)
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Example: Carry Gate (3)
a b Series/Parallel Dual
3-series transistors
2 connections to
c a Vdd
7 floating capacitors
b
f'
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Example: Carry Gate (4)
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Cell Design
Standard Cells
General purpose logic
Can be synthesized
Same height, varying width
Datapath Cells
For regular, structured designs (arithmetic)
Includes some wiring in the cell
Fixed height and width
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Standard Cell Layout
Methodology – 1980s
Routing
channel
VDD
signals
GND
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Standard Cell Layout
Methodology – 1990s
Mirrored Cell
No Routing VDD
channels
VDD
M2
M3
GND
Out
In
2λ
Rails ~10λ
GND
Cell boundary
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Standard Cells
With minimal VDD With silicided VDD
diffusion diffusion
routing
VDD
M2
Out In Out
In
In Out
M1
GND GND
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Standard Cells
VDD 2-input NAND gate
VDD
B
A B
Out
A
GND
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Stick Diagrams
Contains no dimensions
Represents relative positions of transistors
VDD VDD
Inverter
NAND2
Out Out
In A B
GND GND
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Stick Diagrams
X i VDD
X = C • (A + B)
C
i B j A
A B
PDN
A GND
B
C
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Two Versions of C • (A + B)
A C B A B C
VDD VDD
X X
GND GND
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Consistent Euler Path
X i VDD
B j A
GND A B C
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
OAI22 Logic Graph
X PUN
A C
B D D C
X VDD
X = (A+B)•(C+D)
C D
B A
A B PDN
A GND
B
C
D
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Example: x = ab+cd
x x
b c b c
x VDD x VD D
a d a d
GND GND
VD D
GND
a b c d
(c) stick diagram for ordering {a b c d}
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Properties of Complementary CMOS
Gates Snapshot
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
CMOS Properties
Full rail-to-rail swing; high noise margins
Logic levels not dependent upon the relative
device sizes; ratioless
Always a path to Vdd or Gnd in steady state; low
output impedance
Extremely high input resistance; nearly zero
steady-state input current
No direct path steady state between power and
ground; no static power dissipation
Propagation delay function of load capacitance
and resistance of transistors
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Switch Delay Model
A Req
A
Rp
Rp Rp
B
A B Rp
A Rp Cint
Rn CL A
B Rn CL
A Rn Rn CL
Rn
Cint
A B
A
NOR2
NAND2 INV
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Input Pattern Effects on Delay
Delay is dependent on
Rp Rp the pattern of inputs
A B Low to high transition
both inputs go low
Rn CL – delay is 0.69 Rp/2 CL
B one input goes low
– delay is 0.69 Rp CL
Rn
Cint
A
High to low transition
both inputs go high
– delay is 0.69 2Rn CL
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Delay Dependence on Input Patterns
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Input Data Delay
2.5 A=B=1→0 Pattern (psec)
2
A=B=0→1 67
1.5 A=1 →0, B=1
A=1, B=0→1 64
Voltage [V]
1
A=1, B=1→0 A= 0→1, B=1 61
0.5
A=B=1→0 45
0
0 100 200 300 400
-0.5 A=1, B=1→0 80
A= 1→0, B=1 81
Rp Rp Rp
2 A B 2 4 B
Rn Rp Cint
CL 4
2 A
B
Rn Rn Rn CL
2 Cint
1
A A B 1
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Multi-Fingered Transistors
One finger Two fingers (folded)
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Transistor Sizing a Complex
CMOS Gate
B 8 6
A 4 3
C 8 6
D 4 6
OUT = D + A • (B + C)
A 2
D 1
B 2C 2
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Fan-In Considerations
A B C D
A CL Distributed RC model
B C3 (Elmore delay)
C C2 tpHL = 0.69 Reqn (C1+2C2+3C3+4CL)
D C1
Propagation delay deteriorates
rapidly as a function of fan-in –
quadratically in the worst case.
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
tp as a Function of Fan-In
1250
quadratic
1000
500
tpHL tp greater than
250 4 should be
0 tpLH avoided.
2 4 6 8 10 12 14 16 linear
fan-in
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
tp as a Function of Fan-Out
All gates
tpNOR2 tpNAND2 have the
same drive
tpINV current.
tp (psec)
Slope is a
function of
2 4 6 8 10 12 14 16 “driving
strength”
eff. fan-out
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
tp as a Function of Fan-In and Fan-
Out
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Practical Optimization
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Fast Complex Gates:
Design Technique 1
Transistor sizing
as long as fan-out capacitance dominates
Progressive sizing
Distributed RC line
InN MN CL
M1 > M2 > M3 > … > MN
(the fet closest to the
In3 M3 C3 output is the smallest)
charged 0→1
In3 1 M3 CL In1 M3 CLcharged
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Fast Complex Gates:
Design Technique 4
Isolating fan-in from fan-out using buffer
insertion
CL CL
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Fast Complex Gates:
Design Technique 5
Reducing the voltage swing
tpHL = 0.69 (3/4 (CL VDD )/ IDSATn )
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Sizing Logic Paths for Speed
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Buffer Example
In Out
1 2 N CL
N
Delay = ∑ ( pi + g i ⋅ f i ) (in units of τ )
inv
i =1
Gate delay:
d=h+p
effort delay intrinsic delay
Effort delay:
h=gf
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Logical Effort
Logical effort is the ratio of input capacitance of a gate to the input
capacitance of an inverter with the same output current
VDD VDD VDD
A 2 A 2 B 2 B 4
F
F
A 4
A 2
A 1 F
A 1 B 1
B 2
t pNAND
Normalized delay (d)
g= t pINV
p=
d=
g=
p=
d=
F(Fan-in)
1 2 3 4 5 6 7
Fan-out (h)
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Logical Effort of Gates
t pNAND
Normalized delay (d)
g = 4/3 t pINV
p=2
d = (4/3)h+2
g=1
p=1
d = h+1
F(Fan-in)
1 2 3 4 5 6 7
Fan-out (h)
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Add Branching Effort
Branching effort:
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Multistage Networks
N
Delay = ∑ ( pi + g i ⋅ f i )
i =1
Dˆ = ∑ ( g i f i + pi ) = NH 1/ N + P
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Optimal Number of Stages
For a given load,
and given input capacitance of the first gate
Find optimal number of stages and optimal sizing
D = NH 1/ N
+ Npinv
∂D
∂N
( )
= − H 1/ N ln H 1/ N + H 1/ N + pinv = 0
1 / Nˆ
Substitute ‘best stage effort’ h=H
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Logical Effort
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Example: Optimize Path
1 b c
a 5
Effective fanout, F =
G=
H=
h=
a=
b=
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Example: Optimize Path
1 b c
a 5
g=1 g = 5/3 g = 5/3 g=1
f=a f = b/a f = c/b f = 5/c
Effective fanout, F = 5
G = 25/9
H = 125/9 = 13.9
h = 1.93
a = 1.93
b = ha/g2 = 2.23
c = hb/g3 = 5g4/f = 2.59
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Example: Optimize Path
1 b c
a 5
g1 = 1 g2 = 5/3 g3 = 5/3 g4 = 1
Effective fanout, H = 5
G = 25/9
F = 125/9 = 13.9
f = 1.93
a = 1.93
b = fa/g2 = 2.23
c = fb/g3 = 5g4/f = 2.59
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Example – 8-input AND
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Summary
Sutherland,
Sproull
Harris
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu
Homework 5
1. Using the Carry cell design from earlier homework, optimally size the
carry propagate chain for a 16-bit adder to minimize worst case
delay where Cin is driven by a 1u/0.6u inverter and Cout drives a
fanout of 4 such loads. (use logic effort, show your work!)
2. For the problems below, use parameters from class for 0.5um and
use 2x voltages as applicable. Chap 5: problems: 4, 7, 8, 15
3. Chap 6, problems: 2, 4, 5, 7
4. Design the parity tree: c = a xor b xor c xor d in Complementary
Pass Transistor Logic, insert inverters to restore the output swing –
Given input drive from an inverter stage, and an inverter every 2
stages of logic, and inverter output restore, estimate the propagation
time for devices using the AMI 0.5um model.
New (digital) AMI model (for minimum length only!):
n-channel: VT=0.77, λ =0.03, Vsat=1.56V, k=32µ A/V2
p-channel: VT=-0.95, λ =0.03 Vsat=2.8V, k=-16µ A/V2
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Brewer and © Digital Integrated Circuits 2nd
Combinational Circu