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Group members:
Design options :
a) DSPs
b) ASICs
c) FPGA
a) Register Instruction:
It consists of OP, CC, SRC and DST fields
b) Branch Instruction:
It locates addresses in the memory specified by lower four
bits of instruction.
76 54 32 10
OP CC SRC DST
OP Function CC CI
(R0) 00 0
00 (SRC)+CI<=DST
(R1) 01 1
01 (SRC)+DST+CI<=DST
(R2) 10 C
10 DST-(SRC)-CI<=DST
(R3) 11 C’
BRANCH INSTRUCTION
7 6 5 4 3 2 1 0
1 1 C C ADDRESS
When both SEL_L and WR_L are true, the latch is open and a
new data bit is stored
CONCLUSION
FPGA based 8-bit Processor was implemented using VHDL
language