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Microprogrammed
Control Unit
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Table (5-6) Control Functions and Microoperations for the basic Register Reference D7 I’ T3 = r
computer (Mano computer)
IR( I ) = Bi [bit in IR (0-11) that specifies the operation]
r: SC ← 0
Fetch R’T0: AR ← PC
R’T1: IR ← M[AR], PC ← PC + 1 CLA rB11: AC ← 0
Decode R’T2: D0….D7 ← IR (12-14), I ← IR (15), CLE rB10: E←0
AR ← IR (0-11)
CMA rB9: AC ← AC
Indirect D7’IT3: AR ← M[AR]
CME rB8: E←E
Interrupt T0’T1’T2’ IEN (FGI + FGO): R ← 1
CIR rB7: AC ← shr AC, AC(15) ← E, E← AC (0)
RT0: AR ← 0, TR ← PC
CIL rB6: AC ← shl AC, AC(0) ← E, E← AC (15)
RT1: M[AR] ← TR, PC ← 0
INC rB5: AC ← AC+1
RT2: PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0
SPA rB4: If (AC (15)=0) then (PC← PC+1)
Memory Reference
SNA rB3: If (AC (15)=1) then (PC← PC+1)
AND D0T4: DR ← M[AR]
SZA rB2: If (AC =0) then (PC← PC+1)
D0T5: AC← AC ^ DR, SC← 0
SZE rB1: If (E=0) then (PC← PC+1)
ADD D1T4: DR ← M[AR]
HLT rB0: S← 0 (S is a start-stop flip-flop)
D1T5: AC← AC ^ DR, E ← Cout, SC← 0
Input-output
LDA D2T4: DR← M[AR] D7 I T3 =p (common for all input-output instructions)
D2T5: AC← DR, SC← 0 IR( I ) = Bi [bit in IR (6-11) that specifies the instructions]
STA D3T4: M[AR]← AC, SC← 0 p: SC ← 0
BUN D4T4: PC← AR, SC← 0 INP pB11: AC(0-7) ←INPR, FGI ← 0
BSA D5T4: M[AR] ← PC, AR← AR+1 OUT pB10: OUTR ←AC (0-7), FGO ← 0
D5T5: PC← AR, SC← 0 SKI pB9: if (FGI=1) then (PC ←PC + 1)
ISZ D6T4: DR ← M[AR] SKO pB8: if (FGO=1) then (PC ←PC + 1)
D6T5: DR ← DR + 1 ION pB7: IEN ← 1 2
D6T6: M[AR] ← DR, if DR=0 then
IOF pB6: IEN ←0
PC ← PC + 1
S E R IEN FGI FGO DR
3x8
decoder
7 6 5 4 3 2 1 0
D0
...
D7 Control
I logic
gates
T15
...
T0
...
15 14 .... 2 1 0
4x6
decoder
(INR)
4-bit
(CLR)
Sequence
Counter (SC) Clock 3
Ex: Design of Memory Read and Write control circuits
Scanning the table, lead to the control functions for the Read
and Write memory input lines:
Read= R’T1+D’7IT3+(D0+D1+D2+D6) T4
Write= RT1+D3T4+D5T4+D6T6
Memory
Read Write
R
R’ T1
T1 D3
D’7 T4
I D5
T3
T4
Do D6
D1
D2 T6
D6
T4 4
Control Unit Implementation
• Hardwired
Memory Instruction code
Combinational . Control
Sequence Counter
Logic Circuits . signals
• Microprogrammed
CAR: Control Address Register
Memory Instruction code CDR: Control Data Register
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Microprogrammed Control Unit
• Control signals
– Group of bits used to select paths in multiplexers,
decoders, arithmetic logic units
• Control variables
– Binary variables specify microoperations
• Certain microoperations initiated while others idle
• Control word
– String of 1’s and 0’s represent control variables
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Microprogrammed Control Unit
• Control memory
– Memory contains control words
• Microinstructions
– Control words stored in control memory
– Specify control signals for execution of
microoperations
• Microprogram
– Sequence of microinstructions
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Control Memory
• Read-only memory (ROM)
• Content of word in ROM at given address specifies
microinstruction
• Each computer instruction initiates series of
microinstructions (microprogram) in control memory
• These microinstructions generate microoperations to
– Fetch instruction from main memory
– Evaluate effective address
– Execute operation specified by instruction
– Return control to fetch phase for next instruction
Control
Address Control word
memory
(microinstruction)
(ROM)
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Microprogrammed Control
Organization
External Next Address Control
input CDR Control
Generator CAR Memory word
(sequencer) (ROM)
• Control memory
– Contains microprograms (set of microinstructions)
– Microinstruction contains
• Bits initiate microoperations
• Bits determine address of next microinstruction
• Control address register (CAR)
– Specifies address of next microinstruction
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Microprogrammed Control Organization
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Microprogrammed Control
Organization
• Control data register (CDR)- or pipeline register
– Holds microinstruction read from control memory
– Allows execution of microoperations specified by control
word simultaneously with generation of next
microinstruction
• Control unit can operate without CDR
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Microprogram Routines
• Routine
– Group of microinstructions stored in control
memory
• Each computer instruction has its own
microprogram routine to generate
microoperations that execute the
instruction
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Microprogram Routines
• Subroutine
– Sequence of microinstructions used by other routines
to accomplish particular task
• Example
– Subroutine to generate effective address of operand
for memory reference instruction
• Subroutine register (SBR)
– Stores return address during subroutine call
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Conditional Branching
• Branching from one routine to another
depends on status bit conditions
• Status bits provide parameter info such as
– Carry-out of adder
– Sign bit of number
– Mode bits of instruction
• Info in status bits can be tested and actions
initiated based on their conditions: 1 or 0
• Unconditional branch
– Fix value of status bit to 1
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Mapping of Instruction
• Each computer instruction has its own
microprogram routine stored in a given
location of the control memory
• Mapping
– Transformation from instruction code bits to
address in control memory where routine is
located
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Mapping of Instruction
• Example
– Mapping 4-bit operation code to 7-bit address
OP-codes of Instructions
ADD 0000
0001
AND 0010
Control
LDA
memory
Mapping bits 0 xxxx 00 Address
0 0000 00 ADD Routine
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Address Sequencing
• Address sequencing capabilities required
in control unit
– Incrementing CAR
– Unconditional or conditional branch,
depending on status bit conditions
– Mapping from bits of instruction to address for
control memory
– Facility for subroutine call and return
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Address Sequencing
Instruction code
Mapping
logic
Subroutine
Register
Control Address Register (SBR)
(CAR)
Incrementer
select a status
bit
Microoperations
Branch address
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Microprogram Example
MUX
10 0
Computer AR
Configuration Address Memory
10 0 2048 x 16
PC
MUX
15 0
6 0 6 0 DR
SBR CAR
Microinstruction Format
3 3 3 2 2 7
F1 F2 F3 CD BR AD
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Microinstruction Fields
F1 Microoperation Symbol F2 Microoperation Symbol
000 None NOP 000 None NOP
001 AC AC + DR ADD 001 AC AC - DR SUB
010 AC 0 CLRAC 010 AC AC DR OR
011 AC AC + 1 INCAC 011 AC AC DR AND
100 AC DR DRTAC 100 DR M[AR] READ
101 AR DR(0-10) DRTAR 101 DR AC ACTDR
110 AR PC PCTAR 110 DR DR + 1 INCDR
111 M[AR] DR WRITE 111 DR(0-10) PC PCTDR
F3 Microoperation Symbol
000 None NOP
001 AC AC DR XOR
010 AC AC’ COM
011 AC shl AC SHL
100 AC shr AC SHR
101 PC PC + 1 INCPC
110 PC AR ARTPC
111 Reserved
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Microinstruction Fields
Related
With CD
field
BR Symbol Function
00 JMP CAR AD if condition = 1
CAR CAR + 1 if condition = 0
01 CALL CAR AD, SBR CAR + 1 if condition = 1
CAR CAR + 1 if condition = 0
10 RET CAR SBR (Return from subroutine)
11 MAP CAR(2-5) DR(11-14), CAR(0,1,6) 0
Not related
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with CD field
Symbolic Microinstruction
Sample Format Label: Micro-ops CD BR AD
CD one of {U, I, S, Z}
U: Unconditional Branch
I: Indirect address bit
S: Sign of AC
Z: Zero value in AC
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Symbolic Microprogram
• Control memory: 128 20-bit words
• First 64 words: Routines for 16 machine instructions
• Last 64 words: Used for other purpose (e.g., fetch routine and other subroutines)
• Mapping: OP-code XXXX into 0XXXX00, first address for 16 routines are
0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20, ..., 60
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
AND
ADD AC
Arithmetic
logic and DR
DRTAC
shift unit
From From
PCTAR
DRTAR
PC DR(0-10) Load
AC
0 1
Select
Multiplexers
Load Clock
AR 27
Microprogram Sequencer
External
(MAP)
L
I0 3 2 1 0
Input Load
I1 logic S1 MUX1 SBR
T S0
1 Incrementer
I MUX2 Test
S
Z Select
Clock CAR
Control memory
Microops CD BR AD
... ...
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Input Logic for Microprogram
Sequencer
1 L L(load SBR with PC)
From I MUX2 Test
CPU S T for subroutine Call
BR field Input
Z Select I0 logic
of CS I1
S0 for next address
S1 selection
CD Field of CS
Input Logic
I1I0T Meaning Source of Address S1S0 L
S1 = I1
S0 = I0I1 + I1’T
L = I1’I0T
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