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0 S (set) S R Q Q’
1 Q
1 0 0 1
1 1 0 1 (after S = 1, R = 0)
1 0 1 1 0
2 Q’ 1 1 1 0 (after S = 0, R = 1)
0 R (reset) ’ 0 0 1 1
(a) Logic diagram (b) Truth table
CP
2 Q’
4
5
Y
S S S Q
Master Slave
Y’
R R R Q’
CP
MASTER-SLAVE FLIP-FLOP
Flip-Flop on RT54SX-A
(Not hardened)
Master Slave
RT54SX-A SEU Performance
RT54SX-S Latch
(SEU Hardened)
AFB
D B ANQ A Y A A Y A
Y A A
A B Y
S B
C C
BFB
B BNQ A Y B A Y B A
A
A Y
B Y A Y
S B
C
C
CFB
B CNQ
A
A Y C A Y C A
A Y B
S B Y
C
C
G
Flip-Flop Timing: RT54SX-S
Fclock and Fdata are the frequency of the synchronizing clock and
asynchronous data.
• Software is available to automate the calculations with
built-in tables of parameters.
• Not all manufacturers provide data.
Metastability - Sample Data
Sample Metastable Time Data
CX2001 Technology
50 MHz clock, 10 MHz data rate
25
20
15
log10 (MTBF (years))
10
-5
-10
Note: Each flip-flop has its own K1, K2 parameters.
-15
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Slack Time (ns)
Synchronizer (Bad Circuit)
VCC
D Q D Q
DFC1B DF1
EVENT CLK
CLR
CLK
SYSRESET B AND 2A
Y
A
SYSCLK
Metastable State:
Possible Output from a Flip-flop
CLK
Metastable
Q
Metastable State:
Possible Outputs from a Flip-flop
CLK
Q Correct Output
Q
Parallel Registers
D Q Q[3:0]
DATA [ 3 : 0 ]
DF1
CLOCK CLK
4-Bit Parallel Register
D Q
DF1
CLK
D Q
DF1
CLK
D Q
DF1
CLK
D Q Q[3:0]
4-Bit Register With Enable
DATA [ 3 : 0 ]
DF1
CLOCK CLK
D Q
DF1
CLK
D Q
DF1
CLK
D Q
DF1
CLK
Register Files (Simplified)
Register 2
Q
D
Register 1
CLK
Register
Decoder
(AND plane)
Semiconductor
inputs
Word 0
D0
Memory BC BC BC
Word 1
D1
Address
inputs BC BC BC
Decoder Word 2
D2
(AND plane) BC BC BC
Word3
D3
Memory BC BC BC
enable
Read/write
OR plane
Data
outputs
Rad-Hard PROM Architecture
A5 - A11 Row Decoders Memory Array
CE
OE Control Logic I/O Buffers
VPP*
DQ0 - 7
No latches in this architecture
W28C64 EEPROM
Simplified Block Diagram
E2
Row Row Memory
A6-12 Address Address Array
Latches Decoder
CE* Edge
Detect & Timer
WE* Latches