Transistors

Electrical and Electronic Principles

University of Wales Newport 2009 This work is licensed under a Creative Commons Attribution 2.0 License.

The following presentation is a part of the level 4 module -- Electrical and Electronic Principles. This resources is a part of the 2009/2010 Engineering (foundation degree, BEng and HN) courses from University of Wales Newport (course codes H101, H691, H620, HH37 and 001H). This resource is a part of the core modules for the full time 1st year undergraduate programme. The BEng & Foundation Degrees and HNC/D in Engineering are designed to meet the needs of employers by placing the emphasis on the theoretical, practical and vocational aspects of engineering within the workplace and beyond. Engineering is becoming more high profile, and therefore more in demand as a skill set, in todays high-tech world. This course has been designed to provide you with knowledge, skills and practical experience encountered in everyday engineering environments. Contents  Bipolar Transistors  Construction process for a depletion planer transistor  Field Effect Transistors  Metal Oxide Semiconductor Field Effect Transistors (MOSFET)  Credits

In addition to the resource below, there are supporting documents which should be used in combination with this resource. Please see: Green D C, Higher Electrical Principles, Longman 1998 Hughes E , Electrical & Electronic, Pearson Education 2002 Hambly A , Electronics 2nd Edition, Pearson Education 2000 Storey N, A Systems Approach, Addison-Wesley, 1998

Transistors

Bipolar Transistors These are three layer devices, either N-P-N or P-N-P. The operation of each type is the same with the exception that the power supplies are reversed. We will focus on the N-P-N as they are the most common and tend to use positive supplies. The most common way of producing a transistor is by a planar diffusion process. The transistor is effectively created on one face (plane) of a semiconductor material, as shown below:
SiO

n p n
Transistors

Construction process for a depletion planer transistor

p n

ATheexposedpSiliconremoved the surface layercontinues is The mask isanddopant isoverisand the the the an acid photo Agas oxide photo is Oxidesurfaceto thesurface oxide Steam surface light are is applied andprocess surfaceandto A maskinlayer over the topassesand using of the and layeris passedplaced now light which softens The of nowis resist removed over softened photo rich exposed removed a aformed.ofdepletionphoto resist is also removed. then next p Silicon begins to grow. the the remaining layer. resist dissolved region resist

The construction can be thought of as a sandwich of p material as below. B E n p n C

The B base is always the sandwich material The E emitter is the area that is normally a well in the base area The C collector is the substrate into which the other areas are formed.
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C B E

The emitter always is the one with the arrow. For a pnp transistor the arrow points into the base region. B E n p n C

When the junctions are constructed then we will have electron movement similar to the diode and barriers will be set up as below:

Transistors

When the transistor is used, voltages are set up around the device. These voltages are called bias voltages and they are of the following form: ++ V +V 0V +V

0V Note: and the

-V

Base Emitter junction is forward biased Collector Base junction is reverse biased
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This has the following effect on the junction potentials: Emitter Base Collector VCB VBE eeee eeee

As VBE reaches Vj, electrons in the emitter will flood into the base region where they would normally recombine to produce a base current.
Transistors

There are a number of factors that affect the minority electrons in the p-type base region. These are:  During the manufacture of the transistor the base width is made very small and therefore the probability of recombining before reaching the base collector barrier is reduced.  When the transistor is formed either side of the junctions is formed a depletion region where no carries exist. This is due to the movement of electrons from the n into the p and the filling of the holes in the p material. As we have two depletion regions in the base, the area for recombination is therefore reduced.  The reverse bias of the base collector region means that an electron in the base will be accelerated towards the barrier. This reduces the likelihood of recombination.
Transistors

These effects combine to give the following:

Electron flow Emitter Base Collector

The majority of the electrons injected into the base, end up making it across to the collector. The small percentage that recombine form the base current. The ratio of the collector emitter current to the base emitter current gives us the current gain of the transistor.
Transistors

Ic

Ie = Ic + Ib Normally Ic >> Ib and so Ic } Ie

Ib Ie Characteristics. There are two characteristics. The input characteristic this is very similar to the diode characteristic and is a plot of Ib to a base of Vbe. The output characteristic this is a plot of Ic to a base of Vce annotated by Ib (for different values of Ib). A typical plot is shown.
Transistors

2N2222 Characteristic

b = 10 QA b = 8 QA

c (mA)

0 0 2 4 6

b = 0 QA

Wh at can be se e n is th at th e curre nt flowing for a ce rtain value of base curre nt re m ains fairly constant as th e voltage is incre ase d.
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0.5

1.5

b = 6 QA

b = 4 QA b = 2 QA

2.5

Vce (volts)

10

The value of current gain hfe can be given by:

xIc 1.73mA  0.43mA hfe ! ! ! 216 xIb 8QA  2 QA

We will examine how this device is used later in the module.

Transistors

Field Effect Transistors There are two types of FET: The Junction Field Effect Transistor (JFET or JUGFET) This uses a rod of doped silicon with a collar of opposite doped material defused into the rod. Source S Drain D Gate G
Transistors

This can be shown in the following way:

n S p D

This is referred to as an n channel JFET as the conduction from drain to source takes place via a channel of n-type material. If the materials were reversed then this would be a p channel.

Transistors

When the device is constructed there exists a depletion region either side of the junction that is effectively a non-conduction region. This is shown dotted red on the diagram. This effectively reduces the cross sectional area of the channel hence increasing its resistance. If the gate is made negative then little or no current will flow as the junction is reverse biased but this will increase the size of the depletion region and when the gate voltage Vg reaches a certain level the channel cuts off. This is called the cut-off voltage VCUT-OFF

Transistors

If we were to plot the current flow through the device against the gate voltage we would have a graph of the form:
FET characteristic
14 Drain Source current (mA) 12 1 8 6 4 2 6 5 4 3 2 1

Gate voltage Vg (volts)

Transistors

The voltages to the JFET are normally as shown below:

+ive D G -ive 0V S n S 0V

This leads to a modification of the depletion region. Consider a voltage on the gate less than the cut-off with a positive voltage on the drain.

p D +ive

-ive

Transistors

The depletion region gets bigger as we move towards the drain. This is because of the current flowing through the devices causing a voltage drop down its length. The channel is effectively pinched off and this limits the current to a maximum value that is dependent upon Vg. The more negative Vg becomes the smaller the current required to pinch off the channel. Pinching off does not stop the current but it limits it to a maximum value. The output characteristic for such a device is shown.

Transistors

JFET Charcayeristic 2N5484

3.5 3 2.5
Id (mA)

0V -0.2V -0.4V -0. V -0.8V - V

2 1.5 1 0.5 0 0 2 4 6

8 Vds (vol s) 10

The gain of this device will be quoted as an output current over an input voltage.

xIc 3mA  0.45mA Gm ! ! ! 3.19mA / V 0V  0.8V xVb

We will see how this device is used later in the module.

Metal Oxide Semiconductor Field Effect Transistors (MOSFET) The basic operation of these devices depends upon the reduction or creation of a conduction channel through which current will flow. Let us examine a device that depletes an existing channel. N channel depletion MOSFET
SiO Gate Metal Al

Source

Drain

n+

n+ p
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With no voltage on the gate there is a path from the n+ p n p n+ source to the drain and therefore we would have a current flow taking place. If the gate is now made negative then we will have a field set up across the insulating silicon oxide. Note the SiO is very thin usually about 000 , which is 0. Qm and therefore the field will be large even for small voltages. ( V = 0 million V/m) This field will drive away the electrons in the n channel and effectively reduce its cross sectional area. This will increase the channel resistance and reduce the current flow. When the gate voltage is made negative enough the channel disappears and we have cut-off. As with the JFET we will have pinch-off when a current flows through the device and the depletion is distorted.

The characteristic for this device will be very similar to the JFET. The other type of MOSFET starts off with no channel and when a voltage is applied to the gate a channel is created or enhanced. N channel enhancement MOSFET In this device the channel initially with zero gate voltage does not exist. See below
SiO Source Gate Metal Al Drain

n+

n+ p

With no voltage on the gate there is no flow of current between the source and drain. n+ p p p n+ If the gate is now made positive then the large field (once again the SiO is very thin) will attract electrons to the area under the insulating strip. This will result in the channel becoming n type. The greater the positive voltage on the gate, the greater the area of the channel and hence the lower the resistance and the greater the current. We can say that a channel is being enhanced. If we construct p channel devices the opposite polarity is required on the gate to cause the effect.
P channel Depletion Enhancement Positive Negative N channel Negative Positive

Drain D Gate G Gate G

Drain D Gate G

Drain D

Substrate G Source S

(a)

Source S

(b)

Source S

(c)

The three circuit symbols are for a p-channel MOSFET. (b) can be either depletion or enhancement types, whereas (c) represents specifically an enhancement device. In (a) the substrate is understood to be connected internally to the source. For an n-channel MOSFET the direction of the arrow is Transistors reversed.

This resource was created by the University of Wales Newport and released as an open educational resource through the Open Engineering Resources project of the HE Academy Engineering Subject Centre. The Open Engineering Resources project was funded by HEFCE and part of the JISC/HE Academy UKOER programme.

2009 University of Wales Newport

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Transistors