ITRS 2003 Front End Process

ITRS Conference December 2, 2003 Hsinchu, Taiwan

2 December 2003 ITRS Public Conference Tsinchu, Taiwan

FEP Technology Working Groups

Starting Materials: H. Huff, D. Meyers Surface Preparation: J. Butterbaugh, J. Barnett Thermal Films: C. Osburn, H. Huff FEOL Etch: G. Smith, Y. Kim Doping: L. Larson, D. Mercer DRAM Trench Capacitor: Europe FEP, B. Vollmer, M. Gutsche DRAM Stack Capacitor: Japan FEP, M. Kubota, K. Kaneda Flash Memory: M. Alessandri, (Eur)H.K Kang (S. Kor FeRAM: Japan FEP, M. Kubota
2 December 2003 ITRS Public Conference Hsin Chu, Taiwan

FEP- The Grand Challenges

Introduction of many new materials into the CMOS Logic and DRAM process flows (2003-2007)
High k gate dielectric layers Dual metal gates New DRAM storage capacitor structures and materials New substrate materials such as SOI and strained silicon Alternate memory devices and materials, e.g. MRAM, FeRAM

Beyond 2007, the probable introduction and CMOS integration of non-standard, dual-gate MOSFETs e.g. FINFET

2 December 2003 ITRS Public Conference Hsin Chu, Taiwan

MOSFET Scaling- One scenario

2003-2007- Enhanced bulk devices
Strained silicon channels Dual work function metal gates (for p-MOS and N-MOS High-k gate dielectric

2008-2011- Planar fully depleted SOI

Incorporate bulk enhancements Silicon film thickness ~0.4 Lgate Elevated contacts

2012-2018- Fully Depleted Double Gate

2 December 2003 ITRS Public Conference Hsin Chu, Taiwan

Bulk Scaling Challenges- Year 2003-7

2 metals replace dual doped poly High-k replaces Silicon Oxynitride NiSi replaces CoSi2 Strained Si:Ge replaces Si

1/2X every 4-6 years

Drain extension Rs problems Metal/Silicon Contact Rs problems

Gate Length Scaling and 10% 3 CD Control !!!!!

2 December 2003 ITRS Public Conference Hsin Chu, Taiwan

FD SOI Scaling Challenges 2008-2011

Challenges: Dual metal gate integration CD Control (10% 3) Spacer integrity Silicide/Si contact Rs Active Layer t control Hi-k integration Zero Damage Cleaning Box layer t control Drain extension Rs and gate drain overlap Epi-Bulk interface contamination Active layer thickness ~0.4 Lgate, must scale with gate length Box Layer Dual metal gates (nMOS, pMOS) Contact NiSi Sidewall spacer High-k Dielectric Epi Elevated Contact Strained Silicon Active Layer

2 December 2003 ITRS Public Conference Hsin Chu, Taiwan

Double- or Tri-Gate Device Scaling 2011-2018

Metal Gates 1 & 2 Silicon Fin Channel 1

2 Source Drain

Buried Oxide Layer

Gate Dielectric Layer (not shown)

= High N doping = Light P doping

2 December 2003 ITRS Public Conference Hsin Chu, Taiwan

FIN FET Challenges

Challenges: Gate CD Control Metal Gate Integration Fin Thickness control Drain Extension parasitic resistance Silicon/Silicide contact Resistance Sidewall spacer integrity High-k gate dielectric integration Zero damage cleaning Fin Thickness ~0.8 Lgate, must scale with gate length scaling
Sidewall Spacers Source Drain Drain Extensions Gate 1

Gate 2 Hi-k Gate Dielectric Layers

2 December 2003 ITRS Public Conference Hsin Chu, Taiwan

Starting Materials, Near- Term Issues & Challenges

Production Ramp of SOI substrates Production capacity & capability Metrology capability New Substrate Materials Likely Strained silicon on bulk Strained silicon on SOI May be a family of products Site Flatness (FEP Difficult Challenge) Difficult to achieve Wafer/chuck interactions add to overall non-flatness Wafer/Chuck interactions poorly understood
2 December 2003 ITRS Public Conference Hsin Chu, Taiwan

FEP Surface Preparation

Near-tem red wall FEP surface cleaning with very low silicon loss FEP surface cleaning with very low silicon oxide loss Cleaning process for newly introduced materials High-k gate dielectric material(s) Dual work function metal gates DRAM High-k capacitor dielectric materials Strained silicon Cleaning of high aspect ratio structures Stacked and Trench capacitors Vias Fragile structures limit cleaning options
2 December 2003 ITRS Public Conference Hsin Chu, Taiwan

FEP Surface-Preparation, NearTerm Red Wall

Year of Production Technology Node DRAM 1/2 Pitch (nm) Critical Particle Diameter (nm) Critical Particle Count (#//Wafer) Silicon Loss per Cleaning Step (A) Oxide Loss per Cleaning Step (A) 2003 100 50 59 1.2 1.2 2004 hp90 90 45 75 1.0 1.0 2005 80 40 97 0.8 0.8 2006 70 35 64 0.7 0.7 2007 hp65 65 32.5 80 0.5 0.5 2008 57 28.5 54 0.4 0.4 2009 50 25 68 0.4 0.4 Driver DRAM DRAM DRAM Logic Logic

Note: Loss is defined as the average lost per pass, experienced after multiple cleaning passes: e.g. 0.2 Angstrom loss/pass is equivalent to 2 Angstrom loss after 10 cleaning passes Dry strip and clean processes more complex process flows with more cleans, combined with more shallow structures combine to mandate low substrate loss cleaning processes

2 December 2003 ITRS Public Conference Hsin Chu, Taiwan

Front-End Etch
10% 3 control of Gate Length represents a significant near term challenge
Lithography variances contribute to overall variance Resist & Trim variances also contribute

Near Term work-arounds are assume to exist

Design for greater variance Accept lesser binning yields

2 December 2003 ITRS Public Conference Hsin Chu, Taiwan

Etch Challenges

Work-arounds exist

2 December 2003 ITRS Public Conference Hsin Chu, Taiwan

FEP Thermal/Films
Most challenging issue remains the introduction of High-k gate dielectric layers Candidate materials are emerging but none are free of major disadvantages
Interface states at channel and at polysilicon gate electrode Poor charge carrier mobility Threshold voltage shifts CMOS integration challenges

High-k gate dielectric layers require introduction before 2007 for low standby power MOSFETS
Lowered gate leakage allowance (vs 2001 ITRS) for HP drives need High-k gate dielectric in 2007 Gate leakage for Low Standby Power Devices drives need for high-k gate dielectric in 2006

Gate Dielectric Layer Thickness control is emerging as an important challenge STI added for 2003 Roadmap
2 December 2003 ITRS Public Conference Hsin Chu, Taiwan

Thermal/Films Red Walls

Year of Production MPU Physical Gate Length (nm) Low Operating Power Physical Gate Length (nm) Low Standby Power Physical Gate Length (nm) Equivalent Oxide Thickness for MPU/ASIC, Tox (nm) Gate Dielectric Leakage at 100 oC (nA/m) MPU/ASIC Equivalent Oxide Thickness for Low Operating Power Tox (nm) Gate Dielectric Leakage (nA/m) Low Operating Power Equivalent Oxide Thickness for Low Standby Power Tox (nm) Gate Dielectric Leakage (pA/m) Low Standby Power EOT Thickness Control (%3) 2003 45 65 75 1.3 100 1.6 0.33 2.2 3 <4 2004 37 53 65 1.2 170 1.5 1.0 2.1 3 <4 2005 32 45 53 1.1 170 1.4 1.0 2.1 5 <4 2006 28 37 45 1.0 170 1.3 1.0 1.9 7 <4 2007 25 32 37 0.9 230 1.2 1.67 1.6 8 <4 2008 22 28 32 0.8 230 1.1 1.67 1.5 10 <4 2009 20 25 28 0.8 230 1.2 1.67 1.4 13 <4 Driver MPU Low Power LSTP MPU MPU Low Power Low Power LSTP LSTP MPU/ASIC

2 December 2003 ITRS Public Conference Hsin Chu, Taiwan

STI Thermal Films Requirements

Year of Production MPU / ASIC Pitch (nm) MPU Physical Gate Length (nm) STI depth (nm) [X] Trench width at top (nm) [Y] Trench sidewall angle (degrees) [Z} Trench fill aspect ratio SOI STI depth (nm) [AA] SOI Trench aspect ratio 2003 107 45 400 107 >86.2 4.2 36 0.8 2004 90 37 384 90 >86.6 4.8 30 0.8 2005 80 32 367 80 >86.9 5.1 26 0.8 2006 70 28 359 70 >87.2 5.6 22 0.8 2007 65 25 353 65 >87.4 5.9 20 0.8 2008 57 22 339 57 >87.6 6.5 18 0.8 2009 50 20 335 50 >87.9 7.2 16 0.8 Driver MPU MPU Bulk Bulk Bulk Bulk SOI SOI

2 December 2003 ITRS Public Conference Hsin Chu, Taiwan

FEP/Doping
Major challenges continue to surround the achievement of ultrashallow, abrupt, highly activated drain extensions. Drives innovation in ion implantation processes & equipments Drives R&D for very rapid activation processes Attempts at more sophisticated model-based forecasting of Source/Drain requirements have not yet yielded conclusive results S/D requirements highly interactive with overall transistor design S/D requirements for bulk devices are different from SOI and future non-planar double gate devices Drain Extension requirements are listed as target values Modeling of polysilicon gate depletion suggest that metal gates have potential to significantly extend the life of SiON gate dielectric materials

2 December 2003 ITRS Public Conference Hsin Chu, Taiwan

Doping Challenges

2 December 2003 ITRS Public Conference Hsin Chu, Taiwan

HP Logic, Metal Gate Delays Need for High-k Gate Dielectric

Year of Production 2003 2004 2005 2006 2007 2008 2009 Driver MPU Physical Gate Length (nm) 45 37 32 28 25 22 20 MPU Gate Electrode Depletion Effect- Required Gate Dielectric EOT (in nm) to meet device EIT based on Gate Material Choice For the Case of 1E20/cm3 poly doping 1.42 1.32 1.09 0.97 0.88 0.41 0.41 MPU/ASIC 3 For the Case of 2E20/cm poly doping 1.69 1.59 1.38 1.25 1.15 0.74 0.74 MPU/ASIC For the Case of Metal Gate 2.04 1.94 1.74 1.64 1.54 1.15 1.15 MPU/ASIC

Modeling done by H. Gossmann, Axcelis Technologies Inc.

2 December 2003 ITRS Public Conference Hsin Chu, Taiwan

DRAM Stacked Capacitor

Chip Size Model modified, based on survey of DRAM manufacturers Storage cell area increased from prior ITRS DRAM peripheral area decreased from prior ITRS Need for very high-k storage capacitor dielectric materials (e.g. BST) delayed beyond 2009 Aluminum Oxide, Aluminates (e.g. HfAlOx) and Tantalum oxide remain capacitor materials of consideration for the 2003-9 time period Capacitor structure migrates from MIS to MIM in order to avoid challenges regarding capacitor dielectric thickness Total interlevel metal +dielectric (except storage node) is assumed to be 1.08nm at the 180nm node, and to decrease at a rate of 10% every three years. Storage node heights, dielectric constants of high-k materials, and capacitor structures (cylinder, etc) remain unchanged from prior roadmaps

2 December 2003 ITRS Public Conference Hsin Chu, Taiwan