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Bus Organization

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Clock Circuits

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The 8085 has an on-chip clock generator It requires tuned circuit like LC, RC or Crystal or External Clock source as input to generate the clock The T-flip flop divides the frequency by 2 The operating frequency is always half the oscillator frequency

Clock Circuits

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Clock Circuits

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RC Tuned Circuit:

the output frequency is not exactly stable Less cost for components

Clock Circuits

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Cystal Oscillator Circuit: the most stable circuit The 20 pF capacitor assures an accurate start-up frequency

Clock Circuits

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External Clock:

the figure shows how to use an external clock The external clock is applied at X1 input and X2 input is kept open

Demultiplexing AD7 AD0

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AD0-AD7 lines are multiplexed Lower-half address A0-A7 The lower-half address bus must be latched in T1 of the machine cycle to make it available through the rest of the machine cycle. This is done by using an external

Reset Circuit

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On reset, the PC sets to 0000H which causes the 8085 to execute the first instruction in the 0000H address. The reset signal must be held at LOW for 3 clock cycles for a proper reset. The power-on reset circuit ensures the activation of the first instruction from 000H

Reset Circuit

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Upon power-up, RESET IN must remain LOW for 10 ms after the minimum Vcc is reached. Upon power-up or key press, the RESET IN goes low and slowly rises to +5V providing sufficient time to reset. The diode is connected to discharge the capacitor when power supply is cut off After RESET, 8085 loads 0000H in PC register and clears the INTE flag. INTE flip-flop is cleared to disable interrupts. It can be enabled by EI instruction after initial settings. EPROM consisting of monitor program must be located at 0000H to be executed after RESET or Power-up

Generation of Control Signals

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The 8085 provides RD and WR to initiate read or write cycle Read and write signals are separately generated for I/O devices and memory 8085 provides IO/M signal to indicate whether the signal is for I/O or memory Using the IO/M, along with RD and WR it is possible to generate 4 control signals.

Generation of Control Signals

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MEMR (Memory Read) : To read data from memory MEMW (Memory Write) : To write data in memory IOR (I/O Read) : Read data from I/O device IOW (I/O Write) : write data from I/O device

Generation of Control Signals

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The circuit uses OR gates When the output is low only when BOTH inputs are low

Bus Drivers

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Typically, the 8085 buses can source 400 uA and sink 2mA of current 8085 can drive only one TTL load Bus drivers and buffers increase the driving capacity of 8085

Bus Drivers

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UNIDIRECTIONAL BUFFERS 8-bit unidirectional buffer 74LS244 is used to buffer higher address bus. Consists of 8 non-inverting buffers with tri-state outputs Each can sink 24 mA and source 15 mA of current It is Divided into 2 groups 1G and 2G lines control the enabling and disabling of the groups

Bus Drivers

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BI-DIRECTIONAL BUFFER Increases capacity of data bus 74LS245 is a bi-directional buffer also called Octal Bus Transceiver Consist of 16 non-inverting buffers, 8 for each direction with tri-state output Data flow direction is controlled by pin DIR When DIR is high, the flow of data is from A bus to B bus and B to A when low Can sink 24 mA and source 15 mA of current

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Typical Configuration

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