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Address Lines
A memory device or memory chip must have three types of lines or connections: Address, Data, and Control. Address Lines: The input lines that select a memory location within the memory device.
Decoders are used, inside the memory chip, to select a specific location The number of address pins on a memory chip specifies the number of memory locations. If a memory chip has 13 address pins (A0..A12), then it has: 213 = 23 X 210 = 8K locations. If a memory chip has 4K locations, then it should have N pins: 2N = 4K = 22 X 210 = 212 N=12 address pins (A0..A11)
A00 A01 Y00 Y01 Y02 Y03 Location 000 Location 001 Location 002 Location 003
An-2 An-1
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Data Lines
Data Connections: All memory devices have a set of data output pins (for ROM devices), or input/output pins (for RAM devices). Most RAM chips have common bi-directional I/O connections. Most memory devices have 1, 8 or 16 data lines.
Data Input Lines (DI0..DIn-1) k- address lines (A0..Am-1)
Read (RD) Write (WR) Chip Select (CS)
Data Output Lines (DO0..DOn-1) (2m X n) RAM with separate I/P and O/P Data lines
Data Input/Output Lines (D0..Dn-1) (2m X n) RAM with common I/P and O/P Data lines
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Control Lines
Enable Connections: All memory devices have at least one Chip Select (CS) or Chip Enable (CE) input, used to select or enable the memory device. If a device is not selected or enabled then no data can be read from, or written into it. The CS or CE input is usually controlled by the microprocessor through the higher address lines via an address decoding circuit. Control Connections: RAM chips have two control input signals that specify the type of memory operation: the Read (RD) and the Write (WR) signals. Some RAM chips have a common Read/ Write (R/W) signal. ROM chips can perform only memory read operations, thus there is no need for a Write (WR) signal. In most real ROM devices the Read signal is called the Output Enable (OE) signal.
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Some of the address lines select the memory devices that owns the memory location to be read (Step 1a), while the rest point to the required memory location within the memory device.
The processor activates the Read (RD) signal (Step 2).
The selected memory device loads on the data bus the content of the memory location specified by the address bus (Step 3).
The processor reads the data from the data bus, and resets the RD signal (Step 4).
Clock Address Bus Chip Enable Read (RD) Data Bus Step 1a Step 1 Invalid Data Step 2 Valid Data Step 3 Step 4 T1 T2 Valid Address T3
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Some of the address lines select the memory devices that owns the memory location to be written (Step 1a), while the rest point to the required memory location within the memory device.
The processor loads on the data bus the data to be written (Step 2). The processor activates the Write (WR) signal (Step 3).
The data at the data bus is stored in the memory location specified by the address bus (Step 4).
Clock Address Bus Data Bus Chip Enable Write (WR) Step 2 Step 3 Step 4 T1 T2 Valid Address Valid Data T3
Step 1 Step 1a
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Random Access Memory (RAM) A memory device that can be read and written.
Volatile: It looses its data when the power supply is switched-off When the supply is switched-on it contains random data User programs that are loaded from a secondary memory (disk) Temporary data used by programs such as variables and arrays.
Used to store
Programs such as the BIOS. Data such as look tables e.g. the bit pattern of the characters in a dot matrix printer.
Used to store
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EPROM is a type of ROM that can be erased and re-programmed. There are two types of EPROMs: the ultra-violet (UV-EPROMs) and the electrically erasable (EEPROMs) often called the flash memory. UV-EPROMs are erased by inserting the device in ultra violet light and programmed using a special EPROM programmer. UV-EPROMs need to be removed from the PCB in order to erased and programmed.
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RAM Cells
Static RAM (SRAM): The basic element of a static RAM cell is the D-Latch. Data remains stored in the cell until it is intentionally modified. SRAM is fast (Access time: 1ns). SRAM needs more space on the semiconductor chip than DRAM.
SRAM more expensive than DRAM SRAM needs more space than DRAM
Dynamic RAM (DRAM): DRAM stores data in the form of electric charges in capacitors. Charges leak out, thus need to refresh data every few ms. DRAM is slow (Access time: 60ns). DRAM needs less space on the semiconductor chip than SRAM.
DRAM less expensive than SRAM DRAM needs less space than SRAM
SRAM consumes power only when accessed. DRAM needs to be refreshed DRAM is used as the main memory SRAM is used as a Cache
Bit Select Data In
Bit Select
Data Out
D En
Data In
DRAM Cell
Data Out
Write
RAM Cell
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DYNAMIC RAM
DRAM requires refreshing every 2 to 4 ms . Refreshing occurs automatically during a read or write. Internal circuitry takes care of refreshing cells that are not accessed over this interval.
For a 256K X 1 DRAM with 256 rows, a refresh must occur every 15.6us (4ms/256). For the 8086, a read or write occurs every 800ns . This allows 19 memory reads/writes per refresh or 5% of the time.
DRAM technologies
EDO DRAM SDRAM DRDRAM DDR DRAM
Soft errors occur on DRAMs which often require ERROR DETECTION and/or ERROR CORRECTION A DRAM CONTROLLER is required for using DRAM
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Slot 1 SIMM
Slot 2 SIMM
Processor
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Address Decoding
The physical address space, or memory map, of a microprocessor refers to the range of addresses of memory location that can accessed by the microprocessor. The size of the address space depends on the number of address lines of the microprocessor. At least two memory devices are required in a microprocessor system: one for the ROM and one for the RAM. In an 8088/8086 the high addresses in the memory map should always be occupied by a ROM, while the low addresses in the memory map should always be occupied by a RAM. Address decoding is required in order to enable the connection of more than one memory devices on the microprocessor. Each device will occupy a unique area in the memory map. A memory system is not fully decoded if some of the address lines are not used by the address decoding circuit or memory. In this case a memory device will occupy more than one sections in the memory map. This is referred as memory mirroring or memory imaging.
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Solution: 62256 SRAM chips: 256/8 =32 32KX8 Number of chips needed: 128K/32K = 4 Number of address lines: 32K = 25K = 25 * 210 = 215 15 address lines (A0 .. A14)
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18
17
16
15
14
13
A 0 1 0 1 0 1 0 1
M e m o ry M a p C0000 C7FFF C8000 CFFFF D0000 D7FFF D8000 DFFFF RAM 1 RAM 2 RAM 3 RAM 4
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
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62256 A0 D D D
0
62256 A0 D A D
14
62256 A0 D A D
14
62256 A0 D A D
14
D
14
R D W R CS
7
R D W R CS
R D W R CS
R D W R CS
8088 System
RD W R A0 A A A A A
15 16 17 18 19
A 19 IO /M '
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The memory is separated into the High Bank (odd addresses) and the Low Bank (even addresses). The 8086 microprocessor can access either the low bank (D0..D7), or only the high bank (D8..D15), or both banks (D0..D15). The is a need only for separate Bank Write Strobes. When the processor reads from the memory, it always reads both banks, and selects the necessary bank internally.
(BHE') FFFFF FFFFD FFFFB FFFFE FFFFC FFFFA (BLE'/A0) BHE' BLE'(A0) 0 0 1 1 0 1 0 1 Function Example
Both banks enabled (16 bit) MOV [1000H],AX High bank enabled (8 bit) MOV [1001H],AL Low bank enabled (8 bit) MOV [1000H],AL No banks enabled ---------------
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D15 D8 D7 D0 RD WR A0
A1
A1
62256
A0 A14 D0 D7
A1
62256
A0 A14 D0 D7
A1
62256
A0 A14 D0 D7
A15
RD WR CS
A15
RD WR CS
A15
RD WR CS
A15
RD WR CS
8086 System
Y0 A19 A B
Y1
Y2
Y3 1E
Y0 A
Y1 B
Y2
Y3 1E
LS139
LS139
BHE'
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D15 D8 D7 D0 RD BHE' WR A0 A1
A1
62256
A0 D0
A1
62256
A0 D0
A1
62256
A0 D0
A1
62256
A0 D0
A15
A14
D7
RD WR CS
A15
A14
D7
RD WR CS
A15
A14
D7
RD WR CS
A15
A14
D7
RD WR CS
8086 System
Y0 A B
Y1
Y2
Y3 1E
LS139
A19 IO'/M A16 A17 A18 A19
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A2
62256
A0 D0
D0
A2
62256
A0 D0
D8
A2
62256
A0 D0
D16
A2
62256
A0 D0
D24
A16
A14
80386 Processor
RD WR CS
D7 D7
A16
A14
RD WR CS
D7 D15
A16
A14
RD WR CS
D7 D23
A16
A14
RD WR CS
D7 D31
Y0 A B
Y1
Y2
Y3 1E
LS139
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A d d re s s ta cc CS tcd D a ta td f td h
P a ra m e te r A d d r e s s to O u tp u t D e la y C h i p S e le c t to O u tp u t D e la y C h i p D i s e le c t to O u tp u t F lo a t A d d r e s s to O u tp u t H o ld
U n it ns ns ns ns
H ig h Z
T im in g d ia g ra m o f th e 2 7 6 4 E P R O M
A C c h a ra c te ris tic s o f th e 2 7 6 4 E P R O M
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Example
You are asked to interface 8Kx8 bit ROM chips with the following data to a 8088 microprocessor: Chip-select to output delay: 70ns(min) 120ns(typ) 180ns(max) Address to output delay: 230ns(min) 340ns(typ) 450ns(max) Chip deselect to output float: 80ns(typ) 100ns(max) Address to output hold: 80ns(typ) 100ns(max) Assume that buffers have a delay of 20 ns, and latches a delay of 35 ns. The delay of the wires is 20 ns A. Calculate the number of wait states (if needed) B. Draw the corresponding memory read operation timing diagram C. Calculate the number of chips required to create a 32Kbyte ROM D. Specify the memory map starting from address F8000H E. Draw the decoding circuit using NAND gates only F. Draw the decoding circuit using a decoder and NAND gates
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