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PLDs
ROM
PLDs
PLA
CPLD
Interconnctions
CPLDs
FPGA
General Structure
FPGA
The XC4000 CLB contains three separate LUTs Two 4-input LUTS are fed by CLB inputs, and the third LUT can be used in combination with the other two Allows the CLB to implement a wide range of logic functions of up to nine inputs (F1-F4, G1-G4 and H1), two separate functions of four inputs or other possibilities.
Carry Logic
Each cell can be programmed as full adder Carry wires between each cells are hardwired, to provide fast propagation of carry M1 programmed MUX selects the direction of carry M2-M4 MUX allows some of F and G function generator inputs come from carries instead of normal function generators This is also used to implement adder/subtracters, incrementer/decrementers, 2s complemeter, counter etc.
Carry Logic
Ai and Bi from F1 and F2, Ai+1 and Bi+1 from G1 and G2, Ci and Ci+1 are connected to carry propagation lines
CLB as RAM
F an G as input F1=G1, F2=G2.. Provide 4 bit address, C2 and C3 form Data input and C1 as write signal
High density logic along with RAM memory in each device Logic and interconnection is similar to Xilinx FPGAs
LAB
Contains 8 Logic Element (LE) Local interconnect has 22 or more inputs from row interconnect and 8 input feedbacks from LE outputs Each LE has 4 data input from local interconnect as well as additional control inputs LE outputs are routed to row or column interconnect
LE
Each LE has a function generator that implement any of 4 functions using LUT Cascade chain provide connections to adjacent LEs, hence more than four variables can be implemented
Cascade chain
Cascade chain using AND or in OR configuration is:
EAB
EAB
Inputs from row interconnect goes to local interconnect of EAB and serve as either data input or address Internal memory array can be used as RAM or ROM of size 256x8, 512x4, 1024x2 or 2048x1 Several EAB can be used together to form large memory In synchronize mode all memory inputs and outputs are connected to registers In asynchronous mode registers are bypassed