Strained Silicon Technology

TANZEEM IQBAL M.Tech 3rd SEM.(EC&SD) 10LEM301

Overview
Introduction CMOS CMOS Scaling Strained Silicon Why Strained Silicon ? How does it work ? How do we make it ? Drawbacks Conclusions References

Introduction (CMOS History)

The first ever MOSFET transistor was designed by M. M. Atalla, D. Kahng, and E. Labate in late1959

first commercially available integrated circuit made by Fairchild Semiconductor in 1960

4 Intel Pentium 4 released in late 90s

3 Intel 4004 microprocessor in 1971

CMOS
Complementary Metal-oxide-semiconductor field-effect transistors CMOS devices based on sophisticated Si are a fundamental building block for mainstream integrated circuits Technology drivers in the microelectronics industry Due to excellent scalability and integration ability

Moores Law
More and more transistors every year Higher and higher speeds How can we continue to innovate and move faster?

CMOS scaling
Scaling of CMOS devices has reached in nanometers At nanoscale short channel effects occurs SCE will degrade the current drivability and electron mobility of MOSFET Therefore, further improvement is required to go ahead in scaling

Short Channel Effects

As the channel length L is reduced to increase both the operation speed and the number of components per chip, the so-called short-channel effects arise. The short-channel effects are attributed to two physical phenomena:
1. The limitation imposed on electron drift characteristics in the channel, 2. The modification of the threshold voltage due to the shortening channel length.

CMOS scaling

2X transistors every 2 years

Traditional Scaling Era

END OF TRADITIONAL SCALING ERA ~ 2003 Lasted ~40 YEARS

How scaling reduces Mobility ?

As gate length reduces vertical electric field increases This leads to velocity saturation In velocity saturation, drift velocity remains constant after a fixed value of electric field

Need for High Current drivability

In highly interconnected integrated circuits, the high current drivability of the transistors is very important for the circuit performance
Circuit speed is dominate charging/discharging of the load capacitance We need mechanism so that we can increase the current drivability in nanoscale CMOS devices

How to go ahead with scaling ?

To follow Moores Law, we will have to innovate and use materials that results in further scaling without performance degradation

Overview
Introduction CMOS CMOS Scaling Strained Silicon Why Strained Silicon ? How does it work ? How do we make it ? Drawbacks Conclusions References

Strained Silicon
As gate length shrinks, mobility decreases

Method to increase mobility of electrons and holes in the channel of an FET

Tensile and compressive strain applied to channel

Strained Silicon

Strained Silicon
Drain Current Improvement

Strained silicon

How does it work? Basic idea: Change the lattice constant of the material Changes energy band structure!

Strained Silicon

Strained Silicon: Electrons

Strained Silicon: Electrons

Electrical symmetry destroyed by strain Four energy valleys go down in energy, two go up

Change in curvature Reduction in effective mass!

Strained Silicon: Holes

What about the holes?

Uniaxial strain reduces effective mass Biaxial Strain splits LH and HH bands, reduces scattering

Fabrication of strained silicon

Effect was noticed in early 1950s
Generally an effect to be avoided

In recent years, scaling has become more difficult Idea revived at MIT in early 1990s

Fabrication of strained silicon

Two types of strain
Compressive Tensile

Two directions of strain

Uniaxial Biaxial

Biaxial Fabrication
Biaxial techniques pioneered first Method preferred by IBM though examined by all major semiconductor firms Graded SixGe1-x layer grown on silicon substrate
Si Lattice constant = 5.4309 Ge Lattice constant = 5.6575

Biaxial Fabrication
Additional SixGe1-x grown on top of graded layer Thin layer of silicon epitaxially grown on layer of SiGe
SiGe has larger lattice constant than Si (1% larger) Strains the x and y directions

Strained Silicon on Insulator(SSOI)

SiGe on insulator, with silicon epitaxially grown on SiGe
Positive benefits of SOI (lower capacitances, faster switching, lower leakage) as well as benefits of strain

But wouldnt it be good if we could do strained silicon on insulator without SiGe underlayer?

Problems in Biaxial Strain

It takes high germanium content for high hole mobility Less throughput as compared to uniaxial strain Biaxial strain is not cost effective

Uniaxial Strain
Method preferred by INTEL Problems with Biaxial strain

Reexamine the problem

Need strain in the channel of the MOSFET Tensile strain in NMOS Compressive in PMOS

Strain needed in direction from source to drain

Uniaxial Strain
NMOS
Standard fabrication
Cap with SiNx
High temperature deposition Uniaxial Strain Only one direction

10% increase in Idsat

Uniaxial Strain
PMOS
Remove source and drain Selectively grow epi-SiGe in source and drain Nickel Silicide grown on source, drain and gate

Improvements in Idsat of 25%-30%

Recent Strained Silicon Technology Nodes

Overview
Introduction CMOS CMOS Scaling Strained Silicon Why Strained Silicon ? How does it work ? How do we make it ? Drawbacks Conclusions References

Drawbacks
Strain is always a problem
Unwanted strain changes wave functions Work always done to remove the strain Proposals to actually increase the strain instead

Conclusions
Strain in Silicon can increase mobility in NMOS and PMOS FETs Biaxial and Uniaxial strain techniques are developed In use by major players

References
Alexey G. Shapin, Sergey V. Kalinin Strained Silicon as New HighSpeed Technology. 7th International Siberian Workshop And Tutorials, EDM2006 Zoolfakar A.S, Ahmad A. Holes Mobility Enhancement Using Strained Silicon,SiGe Technology. 5th International Colloquium on Signal Processing & Its Application(CSPA) Min Chu, Yongke Sun Strain: A Solution for Higher carrier mobility in Nanoscale Silicon Annual Review of Material Research 2009

K. Mistry, M. Armstrong Delaying Forever: Uniaxial Strained Silicon Transistors in a 90nm CMOS Technology 2004 Symposium on VLSI Technology Digest of Technical Papers M. Reiche O. Moutanabbir Strained Silicon Devices Solid State Phenomena Vols.
156-158 (2010) pp 61-68

A.G.ONeill, S H Olsen Strained Silicon Technology, 2006 IEEE Scott E. Thompson, Guangyu Sun Uniaxial-Process-Induced Strained Si:Extending the CMOS Roadmap IEEE Transactions on Electron devices, vol. 53, no. 5, May 2006

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