8051 Microcontroller

Designing with Microcontrollers

Friday, October 17, 2008

 8051 BLOCK DIAGRAM
I/O

Port 0
A0-A7
ALU PSW SFR
D0-D7

Port 1
I/O

A B

Port 2
I/O
A8-A15

DPTR
PC DPH ROM
I/O

Port 3
DPL INT
CNTR
SERIAL
RD/WR

Friday, October 17, 2008

 ~EA
ALE System Timing BYTE / BIT SFR
ADDRESSIBLE
PSEN
System Interrupt IE
XTAL1
Timers RB3 IP
XTAL2
RB2 PCON
RESET Data Buffers
SBUF
VCC Memory Controls RB1
SCON
GND
RB0 TCON
TMOD
TL0
TH0
TL1
TH1

INTERNAL RAM STRUCTURE

Friday, October 17, 2008
 A* B* IP* IE* TMOD TCON*
E0 F0 B8 A8 89 88

MATH REGISTERS INTERRUPT REGISTERS TIMER CONTROL REG

THO TLO TH1 TL1

8C 8A 8D 8B

TIMER / COUNTER REGISTERS

SCON* SBUF PCON PSW*

98 99 87 D0

SERIAL DATA REGISTERS FLAGS

SP
81

Friday, October 17, 2008

 DPTR
DPH DPL PC
83 82

PORT 0* PORT 1* PORT 2* PORT 3*

LATCH LATCH LATCH LATCH
80 90 A0 B0

Friday, October 17, 2008

 PSW

CY AC F0 RS1 RS0 OV - P

CY Carry Flag used in arithmetic and Boolean operation

AC Auxiliary Carry, used in BCD arithmetic
F0 User Flag 0
RS1 Register Bank select bit 1
RS0 Register Bank select bit 0
RS1 RS0
0 0 Select Register Bank 0
0 1 Select Register Bank 1
1 0 Select Register Bank 2
1 1 Select Register Bank 3
OV Overflow Flag used in arithmetic instructions
P Parity, shows parity of register A; 1 = Odd Parity

Friday, October 17, 2008

 TIMERS & COUNTERS
THE TIMER CONTROL (TCON)
7 6 5 4 3 2 1 0

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

1 TF1 Timer 1 Overflow flag. Set when timer rolls from all 1s to 0. Cleared when processor
vectors to execute interrupt service routine located at program address 001Bh.
2 TR1 Timer 1 run control bit. Set to 1 by program to enable timer to count; cleared to 0 by program to
halt timer. Does not reset timer.
3 TF0 Timer 0 Over flow flag. Set when timer rolls from all 1s to 0. Cleared when processor
vectors to execute interrupt service routine located at program address 000Bh.
4 TR0 Timer 0 run control bit. Set to 1 by program to enable timer to count; cleared to 0 by program to
halt timer. Does not reset timer.
5 IE1 External interrupt 1 Edge flag. Set to 1 when a high-to-low edge signal is received on port 3 pin
3.3 (INT 1). Cleared when processor vectors to interrupt service routine located at program
address 0013h. Not related to timer operations.
6 IT1 External interrupt 1 signal type control bit. Set to 1 by program to enable external interrupt 1 to
be triggered by a falling edge signal. Set to 0 by program to enable a low-level signal or external
interrupt 1 to generate an interrupt.
7 IE0 External interrupt 0 Edge flag. Set to 1 when a high-to-low edge signal is received on port 3 pin
3.2 (INT 0). Cleared when processor vectors to interrupt service routine located at program
address 0003h. Not related to timer operations.
0 IT0 External interrupt 0 signal type control bit. Set to 1 by program to enable external interrupt 0 to
be triggered by a falling edge signal. Set to 0 by program to enable a low-level signal or external
interrupt 0 to generate an interrupt.
Friday, October 17, 2008
 THE TIMER MODE CONTROL (TMOD)
7 6 5 4 3 2 1 0

Gate C/T M1 M0 Gate C/T M1 M0

Timer 1 Timer 0

7/3 Gate OR gate enable bit which controls Run/ Stop of timer
6/2 C/T Set to 1 by program to make timer act as counter
5/1 M1 Mode select bit 1
4/0 M0 Mode select bit 0
M1 M0 Mode
0 0 0
0 1 1
1 0 2
1 1 3

Friday, October 17, 2008