DIFFERENTIAL

VOLTAGE CURRENT
CONVEYOR (DVCC)
INTRODUCTION
Introduced in 1968 by Smith and Sedra.
Current conveyors have proved to be
functionally flexible and versatile, rapidly
gaining acceptance as both a theoretical
and practical building block .
Conventional second generation current
conveyors (CCII) have an apparent
disadvantage of having only one voltage
input terminal .
In many applications such as analog signal
processing , automatic control, and
instrumentation system processing
differential voltage signal are very common.
To overcome this drawback, the differential
voltage current conveyor was proposed.

IDEAL DVCC

The DVCC is a five-port building and described by
the following matrix equation:

V
X
0 1 -1 0 0 I
X

I
Y1
0 0 0 0 0 V
Y1

I
Y2
= 0 0 0 0 0 V
Y2

I
Z1
1 0 0 0 0 V
Z1

I
Z2
-1 0 0 0 0 V
Z2


Symbol of DVCC
Current and voltage relation for DVCC are as follows
V
X
=V
Y1
-V
Y2

I
Y1
=I
Y2
=O
I
Z1
=+I
X

I
Z2
=-I
X

Where:
V
Y1
= voltage at node Y
1

V
Y2
= voltage at node Y
1

V
X
= Voltage at node X
I
X
= current at node X
I
Z1
= current at output node Z
1

I
Z2
= current at output node Z
2


Ideal representation of DVCC

CMOS IMPLEMENTATION OF DVCC

DC ANALYSIS
Various Voltage Responses
V
X
vs. V
Y2
(for V
Y1
=0)
output current vs. V
Y2
(for V
Y1
=0)










Frequency Response of various
Voltages
AC Analysis of DVCC





Frequency Response of various
Currents

Voltage waveforms at f=100KHz

Current waveform at f=100 KHz

PSPICE simulation is also carried out for
sinusoidal inputs.
The THD was found as 1% up to the
frequency of 200MHz.

PROPOSED MODIFIED DVCC
Modified DVCC is similar as DVCC. But it
has multi outputs (two Z
+
Stages and one
Z
-
stage) as shown in fig.
The gain of second Z
+
stage and Z
-
stage
is five times of first Z
+
stage .

Schematic Diagram of Modified
DVCC

Current and voltage relation for Modified DVCC are as
follows
V
X
=V
Y1
-V
Y2

I
Y1
= I
Y2
=0
I
Zi+
=K
1
I
X

I
Zj-
=K
2
I
X

Where: i= 1,2 and j=1
V
Y1
= voltage at node Y
1

V
Y2
= voltage at node Y
2

V
X
= voltage at node X
I
X
= current at node X
I
Zi+
= current at out put node Z
+

I
Zj-
= current at out put node Z
-

CMOS realization of modified dvcc
DC Analysis

:




Various Voltage Responses
V
X
vs V
Y2
(for VY1=0)

output current vs. V
Y2
(for V
Y1
=0)

: Frequency Response of various
voltages










Frequency Response for Various
currents













The THD was found as 1% up to the frequency of 200 MHz.








Voltage Waveform at f = 100 KHz


sinusoidal signal of 100mv is applying at V
Y1
terminal
and sinusoidal signal of 60mv is applying at V
Y2

terminal, 40mv appears at Vx terminal


































Current Waveforms at f=100 KHz

Ix is conveyed to I
Z1+
terminal with the same gain andis
conveyed to I
Z2+
, I
Z1-
terminals with five times of gain and
with five times of gain in inverted manner respectively and
thus verify the circuit.























Symbolic representation of DVCC
with parasitic






NON IDEAL ANALYSIS AND
PARASITIC STUDY


At high frequency of operation, effect of parasitic capacitance
come into account and affect the performance of DVCC.
All the transistor are biased in saturation region only capacitance
between gate and source having value c
gs
=2/3c
ox
WL
eff
will be
effective capacitance.
At Y
1
, cgs of transistor M3 will be effective capacitance .
Y
2
also shows the similar parasitic.
While at terminal X there will be a parasitic capacitance C
X
in
parallel with parasitic resistance R
X
. Capacitance C
X
will be equal
to the parasitic capacitance c
gs
of transistor M4.
While at terminal Z+, R
Z+
will be equal to the resistance R
o8

R
o12
, while C
Z+
will be equal to the summation of capacitance
C
gdo8
and C
gdo12
.
This parasitic characteristic will also visible at terminal Z-.


NOVEL CURRENT MODE
QUADRATURE
OSCILLATOR CIRCUITS

Here eight new current mode quadrature
oscillator circuits using DVCC and the new
modified DVCC using grounded passive
elements are proposed.
Each circuit gives the four quadrature
current outputs of equal amplitude and
exhibits high output impedance, which is
desirable for current mode applications.
These circuits are implemented and the
results are verified through simulation.

. The proposed circuits are based on the
newly developed differential-voltage current
conveyor (DVCC), an active element with
differential input terminals.
The proposed quadrature oscillator circuits
employ one modified DVCC and two DVCCs .
It is to be further noted that in all the
proposed circuits DVCC3 is the modified one
whereas DVCC1 and DVCC2 are the ones
with unity current gain .

















Eight proposed Current Mode
Quadrature Oscillator (CMQO)
circuits

Circuits Analysis

CMQOs (1 IV) shown in Fig. are
characterized by equation



It is clear from equation that the
frequency of oscillation (FO) and the
condition of oscillation (CO) are as follows
:




FO :

The four quadrature current outputs (I
1
, I
2
, I
3
and I
4
) of the proposed circuits (CMQOs I
IV), are related as:
I
4
= -I
3
, I
2
= -I
1

I
3
= -jkl
2
, k = R
2
C
2

For k = 1, all the four quadrature outputs, which are given in above equation have equal
amplitude. Note that besides maintaining the CO as the circuit has to be designed so that
R
1
> R
2
since the FO contains a involving (R
1
-R
2
).
CMQOs (V VIII) are characterized by equation .

2 3 2 2 1
3 2 `1 1 1 1 3 1 2
1 1
0
C R C C
s s
C R R C C CC R R
| |
+ + =
|
\ .

The frequency of oscillation and condition
of oscillation is given in equation below:
The four quadrature current outputs (I
1
,
I
2
, I
3
and I
4
) of the proposed circuits
(CMQOs V VIII), depicted in Fig. 3.2,
are related as:
I
4
= -I
3
, I
2
= -I
1
(3.7)
I
3
= -kl
2
, k = C
3
/C
2
(3.4)

For k = 1, all the four quadrature outputs,
which are given in above equation have
equal amplitude.

Effects of DVCC Parasitics
Analogous to the second-generation current
conveyor (CCII), the DVCC has a small parasitic
resistance R
X
at port X .
The parasitic resistance at the X terminal of the
DVCC (R
X
) can be absorbed as a part of the main
resistance.
As the value of R
X1
is much smaller then the
external resistors (R
1
, R
2
, R
3
) so the effect will be
negligible .
The DVCCs with only a capacitor at X terminal
pose high frequency limitation.
The effects of the capacitors at port Y and Z of
the DVCCs are also negligible because these
capacitors are quite small as compared to the
external capacitors.

SIMULATION RESULTS
The PSPICE simulations were performed
using the CMOS realization of DVCC with
0.5, level 3 MOSFET parameters .
The supply voltages used were 2.5V.
The circuit was designed with: C1 = C2 =
30pF, R1 = 10.4K, R2 = 1.59K, R3 =
10K.
The designed frequency of oscillation is
1.22 MHz.
The FO as obtained from simulations is
1.20MHz, which is 1.6% in error with the
designed value,
The power consumption was found to be
17.5mW. The THD of the proposed circuit
at all outputs is within 1.5%, which is low.

The FO is found to vary from 0.18MHz at
R
2
= 9K to 1.59MHz at R
2
= 1K, which
shows variation in FO for variation in R
2

and FO can be independently control with
the help of R
2
, without any change in CO.
CONCLUDING REMARKS

All the proposed eight circuits enjoy the use of
grounded components.
All the four canonical circuits possess non-
interactive tuning features.
The results show small errors in frequency and
low THD.
The new circuits also possess wide frequency
tuning through a single resistor.
The non ideal study along with parasitic study
has also been carried out.
The new proposed circuits are attractive for IC
implementation
NOVEL VERSATILE QUADRATURE
OSCILLATOR CIRCUITS


Here eight new canonical and non-canonical
circuits for realizing second-order versatile
quadrature oscillators (VQOs) are proposed.
Each circuit employs three differential voltage
current conveyors and all grounded passive
components , ideal for IC implementation.
Some of the circuits possess non-interactive
frequency control.
All these circuits are based on simpler topology
then previous one and provide two more
quadrature voltage outputs.
The effects of parasitic are also less, as
compared to the previous CMQO
S
.
PSPICE simulations using 0.5 CMOS
parameters confirm the validity and practical
utility of the proposed circuits.

Moreover oscillators with quadrature output
(with 90
0
phase shift) find application in
communication and instrumentation systems.
Another important feature desired from
current mode circuit is high output
impedance for ease of cascading .
The proposed circuits exhibit non-interactive
frequency control , provided for
progressive Quadrature outputs at high
impedance nodes.
All these feature mark the new circuits
a unique addition to the already available
literature on the subject.
Eight proposed versatile Quadrature Oscillator (VQO) circuits
VQO
S
(I-IV) shown in Fig. are characterized by equation:

S
2
+ S[(1/C1R1)-(1/C2R3)]+1/C1C2R2R3= 0
It is clear from equation that the frequency of oscilation
(FO)
and the condition of oscillation (CO) are follows :
FO:
0=
=


CO:C1R1C2R3


FO can be varied independent of CO by R
2

The four quadrature current outputs ( I
1
, I
2
, I
3
and I
4
)

of the
proposed circuits (VQO
S
I- IV )
,
are related as

I
4
= - I
3
, I
2
= -I
1

I
3
= jkl
2
, k= C
2
R
2

For k=1, all the four quadrature current outputs, which area
given in equation
have equal amplitude.
VQO
S
(V VIII) are characterized by equation.
S+S1/C3R2((C3R2/C1R1)-(C2/C1))+1/(C1C3R1R2)=0


FO:
0=
=

V
1
=-j
k
V
2
, k =C
3
R2
For k=1, both the two quadrature voltage outputs ,which are
given in equation have equal amplitude .
The four quadrature circuit outputs (I
1
, I
2
, I
3
and I
4
) of the
proposed
Circuits (VQOV VIII), are related as
I
4
=-I
3
, I
2
=-I
1

I
3
=kl
2
, k=C
3
/C
2

Analogous to the secondgeneration current
conveyor (CCII), the DVCC has a small
parasitic resistance R
X
at port X and high
output impedence at Z.
The parasitic resistance at the X terminal of
the DVCC (R
X
) can be absorbed as a part of
the main resistance .
The effects of the capacitors at port Y and Z
of the DVCCS are also negligible because
these capacitors are quite small (and process
dependent) as compared to the external
capacitors.
The circuits are not adversely affected by the
parasitic capacitances and X-terminal

COMPARATIVE STUDY

VQO-I is found to be best quadrature
oscillator with the less transistor count ,
all grounded element ,canonical and with
non interactive control of frequency of
oscillation.
While VQO-VIII is found to be the most
complicated quadrature oscillator.

SIMULATION RESULTS


The PSPICE simulations were performed
using the CMOS realization of DVCC with
0.5, level 3 MOSFET parameters.
The designed frequency of oscillation is
1.37MH
Z
.
The FO as obtained from simulations is
1.36MH
Z
, Which is 0.7% in error with the
designed value.
The power consumption was found to be
15mW.
The THD of the proposed circuit at all
outputs is within 1.0%, which is low.

Two quadrature voltage output of
VQO1 circuit
FO can be independently control
with the help of R2 , without any
change in CO
POSSIBLE APPLICATIONS OF
QUADRATURE OSCILLATOR


The major area of use of quadrature oscillator is in
communication and instrumentation system.
Mainly, in telecommunication as in quadrature mixer, signal side
band generators, as for measurement purposes in vector
generators and in measurement purpose for selective voltmeters.

Another use of quadrature oscillators in RF application as a
power supplier. And some other possible applications of
quadrature oscillators as in universal clock recovery network for
QPSK modems, in carrier recovery .

Apparatus for responding to an interrogation signal , in
synchronous tracking AM receiver, for driving an antenna coil and
generating a clock signal, in Low power RF amplifying a cellular
radio signals.



CONCLUSION
The dissertation presents the description of
the DVCC and its verification results, along
with the new proposal of modified DVCC.
The non idealities and parasitic study (with
R
X
calculation) of the modified DVCC is also
carried out.
The dissertation presents 16 new quadrature
oscillator circuits. Eight new (chapter 2)
second order current mode quadrature
oscillators (CMQO
S
) realizing four quadrature
current outputs impedance .
The first four circuits of CMQO
S
provide single
resistance control facility without affecting
the condition of oscillation.
The variation in the frequency of oscillation of CMQO
S
due to
change in resistance (from 1K to 10K) is also described and
verified through results.
Another set of eight new circuits (chapter 4) of versatile
quadrature oscillators (VQO
S
) are further proposed.
All the new circuits of VQO
S
realize four quadrature current
outputs and two quadrature voltage outputs with low THD .
The first four circuits possess non-interactive control of frequency
of oscillation.
The circuits show a wide variation in frequency through resistor
variation

These circuits of VQO
S
are simpler and advantageous then the
CMQO
S
.
The non ideal analysis and parasitic study is also given.
The new proposed circuits are verified through PSPICE simulation
using 0.5m CMOS parameters.


Scope for Further Work

All the circuits presented uses grounded capacitors, which
are ideal for IC implementation.
The resistors used in the presented circuit are also in
grounded from.
These resistors can be replaced by their active equivalents
in MOS technology with the added advantage of tunability
through external control voltage .
The DVCC and modified DVCC employed in the circuits are
also in CMOS technology.
Thus the proposed quadrature oscillator circuits are
compatible in CMOS technology.
Further R
X
can be controlled with the help of V
BB
(bias
voltage).
Thus, frequency parameters can be controlled with the help
of V
BB
.



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