You are on page 1of 21

Department of Technical Education

Andhra Pradesh
Name : P. Srinivasa Rao
Designation : Lecturer
Branch : Electronics & Communication Engg.
Institute : Andhra Polytechnic, Kakinada
Year/Semester : III semester
Subject : Digital Electronics
Subject code : CM-305
Topic : Counters & Registers
Duration : 50mts
Sub topic : UP/DOWN counter
Teaching Aids : PPT Diagrams
CM305.53 1
OBJECTIVES

On completion of this period, you would be able


to

• Draw the circuit diagram of Up-down counter.

• Know the principle of operation of the Up-down counter.

• Draw the timing diagram of Up-down counter.

CM305.53 2
Recollection
1. What is up counter?
It is the counter which is capable of progressing in the
forward direction, through a certain counting sequence.

Ex: A 2-bit binary counter with a upward counting


sequence of 0,1,2,3.

2. What is down counter?


It is the counter which is capable of progressing in the
reverse direction, through a certain counting sequence.

Ex: A 2-bit binary counter with a downward counting


sequence of 3,2,1,0.
CM305.53 3
3 . What is meant by Edge triggering?
It means that the flip flop is changing the state either
at the positive edge (raising edge) or at the negative
edge (falling edge) of the clock pulse.

4. Draw the clock pulse showing positive & negative


edge triggered type.

Rising Falling edge


edge

CM305.53 4
CM305.53 5
UP/DOWN SEQUENCE FOR A 3-BIT BINARY
COUNTER

Clock UP QC QB QA DOWN
pulse
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1CM305.531 1 6
Principle of 3-bit UP/DOWN counter

• UP/DOWN is a control input which determines the


basic operation of the counter.

• When UP/DOWN input is at high UP mode of operation is to


be performed .

• When UP/DOWN input is at low DOWN mode of operation is


to be performed.

• The out put of the counter is given by Q= QC QB QA

CM305.53 7
• In this counter flip flop in the lower order position is
complemented with every clock pulse .

• From the truth table notice that QA changes for every


clock pulse for both UP/DOWN sequences.

• First flip flop toggles on each clock pulse because of J


&K inputs are at HIGH .

CM305.53 8
UP MODE OF OPERATION

• When QA=1, QB changes its state on the next clock


pulse.

• When the first clock pulse occurs, QA=1&QB = 0.

• At the second clock pulse QA=0 & QB=1.

CM305.53 9
• The output of Qc changes its state on the next
clock pulse when QA=QB=1.

• When the fourth clock pulse occurs Qc changes its


state from 0 to 1.

CM305.53 10
CONDITIONS FOR UP MODE OF OPERATION:

• Control input UP/ DOWN must be at HIGH.

• J&K inputs of second flip flop must be equal to 1 under the


condition
JB=KB=QA.UP.

• Similarly the inputs of the third flip flop must be equal to 1


under the condition
JC=KC=QA.QB.UP.

CM305.53 11
DOWN MODE OF OPERATION:

• The output QB changes its state on the next clock pulse


when QA=0.

• Qc changes its state on the next clock pulse when


QA=QB=0.

The above two changes can be observed from the truth


table.

CM305.53 12
CONDITIONS FOR DOWN MODE OF OPERATION

• UP / DOWN input must be at low.

• J and K inputs of second flip flop must be equal to 1 under


the condition
JB=KB=QA.DOWN

• J and K inputs of the third flip-flop must be equal to 1 under

the condition JC=KC=QA.QB.DOWN

CM305.53 13
TIMING DIAGRAM

CM305.53 14
Note from the Timing diagram

• Counter starts in the all 0’s state and is positive edge


triggered.

• Up operation is performed upto the trailing edge of the


forth clock pulse .

• Down operation is performed from fourth clock pulse.

CM305.53 15
SUMMARY

• the circuit diagram of Up-down counter.

• the principle of operation of the Up-down counter.

• the timing diagram of Up-down counter.

CM305.53 16
QUIZ

1. The counter which is capable of progressing in the


forward direction is called

a) up counter

b) Down counter

c) decade counter

d) ripple counter

CM305.53 17
1. Preset and clear inputs are called

d) synchronous inputs

f) asynchronous inputs

c) control inputs

d) timing inputs

CM305.53 18
3. In the case of up operation Up / Down pin becomes

a) 0

b) 1

c) High

d) both b & c

CM305.53 19
4. In Mod-16 up counter the no. of flip-flops are

a) 1

b) 2

h) 3

j) 4

CM305.53 20
Questions

1. Draw the logic circuit of up/ down counter

3. Explain the working of up/down counter

5. Is the up/ down counter can be classified as


synchronous counter of asynchronous counter?

CM305.53 21