Adv Pres SR Comm

8031 MlC8CCCn18CLLL8S
SL8lAL CCMMunlCA1lCn
lnLerrupLs
rof AmlL u ved
AssL rof Pead
LlecLrlcal Lnglneerlng ueparLmenL
Cardl college of Lnglneerlng and 1echnology
8a[koL ( Cu[araL)
12,12,2011 BL VI ,LLLC1RICAL, ADVLD 2010
1
aslcs of serlal communlcaLlon
Parallel: transIers eight bits oI data simultaneously over eight data
lines
expensive - short distance Iast
Serial : one bit at a time is transIerred over a single line
cheaper long distance-slow
Ser|a| transm|ss|on ara||e| transm|ss|on
wlres 8 wlres
roblem of lnLer symbol lnLerference
Small L C less bandwldLh and less daLa
raLe
S/n S/n Cl A8ALLLL More nolse less S/n
PlCP l1 8A1L uS0480MlLs/sec
!ISO
SI!O
asics oI serial communication
In simplex transmission such as with printers, computer only sends data.
II the data can be transmitted and received, it is a duplex transmission. Duplex can be
halI or Iull duplex, depending on whether or not the data transIer can be simultaneous.
NO MODULA1ION RLQUIRLD lOR SMALL DIS1ANCL. MODLM CAN BL USLD
lOR LONG DIS1ANCL.
aslcs of serlal communlcaLlon
W Serial data communication uses two methods:
Asynchronous and synchronous.
W The synchronous method transIers a block oI data
(characters) at a time , block oriented data transIer
W The ,synchronous method transIers a single byte at a time
W Special Ics. Character oriented data transIer, Iraming is
necessary.
W D@ (unlversal asynchronous 8ecelver LransmlLLer)
W DS@ (unlversal synchronousasynchronous 8ecelver
LransmlLLer)
ackag|ng Data
Start and stop b|ts
In asynchronous transmission when there is no transIer the signal is high
Transmission begins with a start (low) bit LS Iirst
Finally 1 stop bit (high) old systems had 2 bits as stop bit
For data integrity parity bit can also be included
Data transIer rate (baud rate) is stated in bps (the rate oI data transIer in serial data
communication is stated in bits per second) baud rate modem terminology no oI signal
change per second, many times in 1 signal change many bits can be transIerred, here
baudrate and bps are same.
8S S1AnuA8u
W 1 ls Lo 3v 0 ls + Lo +3v
W u1L(uA1A 1L8MnlAL LCulMLn1) CCM C8 1L8MlnAL
W uCL (uA1A CCMMunlCA1lCn LCulMLn1) MCuLM
W D@ (data term|na| ready) Jhen Lermlnal ls Lurned on lL sends ouL
slgnal u18 Lo lndlcaLe LhaL lL ls ready for communlcaLlon
W DS (data set ready) Jhen uCL ls Lurned on and has gone Lhrough
Lhe selfLesL lL asserL uS8 Lo lndlcaLe LhaL lL ls ready Lo
communlcaLe
W @S (request to send) Jhen Lhe u1L devlce has byLe Lo LransmlL lL
asserL 81S Lo slgnal Lhe modem LhaL lL has a byLe of daLa Lo
LransmlL
W C@S (c|ear to send) Jhen Lhe modem has room for sLorlng Lhe
daLa lL ls Lo recelve lL sends ouL slgnal C1S Lo u1L Lo lndlcaLe LhaL lL
can recelve Lhe daLa now
W DCD (data carr|er detect) 1he modem asserLs slgnal uCu Lo lnform
Lhe u1L LhaL a valld carrler has been deLecLed and LhaL conLacL
beLween lL and Lhe oLher modem ls esLabllshed
W (r|ng |nd|cator) An ouLpuL from Lhe modem and an lnpuL Lo a C
lndlcaLes LhaL Lhe Lelephone ls rlnglng lL goes on and off ln
synchronous wlLh Lhe rlnglng sound
MAx LlnL u8lvL8(8S11L)
8031 Serlal CommunlcaLlon
W The 8051 has a single Iull duplex (means it can transmit and receive data at a
time) serial port that can be used Ior either asynchronous or synchronous
communication.
W Facilities with 8051 Ior serial communications
S&F holds data
SCON control communication
PCON control data rate
RxD(P3.0) & TxD(P3.1)
W The port has 4 modes oI operation:
Mode 0: Synchronous at 1/12 oscillator Irequency.
Mode 1: 10 bit Asynchronous - variable baud rate.
Mode 2: 11 bit Asynchronous -1/32 OR 1/64 oI the oscillator Irequency.
Mode 3: 11 bit asynchronous - variable rate.
MODE 2 AND3- M&LTIPROCESSOR MODE
serlal communlcaLlon block dlagram
In the memory map we have serial buIIer special Iunction register (S&F) at
location 99H.
&nlike any other register in the 8051, S&F is in Iact two distinct registers -
the write-only register and the read-only register.
Transmitted data is sent out Irom the write-only register while received data is
stored in the read-only register.
There are two separate data lines, one Ior transmission (TXD)(P3.1) and one
Ior reception (RXD)(P3.0). ThereIore, the serial port can be transmitting data
down the TXD line while it is at the same time receiving data on the RXD line
I
N
1
L
R
N
A
L

B
U
S
\RI1L ONL\
,!ISO,
RLAD ONL\
,SI!O,
1XD
RXD
SBUl ,99h,
Byte
bit
bit
Byte
15
lRAMING
DLlRAMING
S&F register
W Data to be transmitted via the TXD line must be placed in S&F
register.
W S&F holds the byte oI data when it is received by 8051 RXD
line.
W MOV S&F, #45H - this sends the byte 45H down the serial
line
W MOV A, S&F - this takes whatever data was received by the
serial port and puts it in the accumulator
W Once byte is written in S&F, it is Iramed with the start and stop
bits and transIerred serially via the TXD pin.
W When the bits are received serially via RXD, the 8051 deIrames
it by eliminating the stop and start bits and then placed it in
S&F register.
Power confroI regisfer (PCOM)
W luLL MCuL
W CCn01
W CLCCk SlCnAL CA1Lu Cll 1C Cu nC1 1C Cn CPl L8lPL8AL
W Cu S1A1L lS 8LSL8vLu
W S C SJ A C1PL8 8LClS1L8S MAln1Aln uA1A
W C81 lnS PCLu LCClCAL S1A1uS
W ALL SLn 1
W Lxl1 l8CM luLL MCuL
AC1lvA1L LnALLu ln1L88u1
8LSL1
21
owerDown Mode
W PCON.1 1, causes power down mode
W The ALE and PSEN output are held low
W The reset that terminates Power Down
W Internal clock Irozen to entire Microcontroller (CORE &
PERIPHERAL)
W Program is not dead
W Cpu starts Irom next instruction where PD was invoked
W Port values are not changed
W Vcc can be reduced to 2V, but has to be restored beIore PD is exited.
W For 8051, active mode current 25mA, idle mode current 6.5mA and
power down mode current 100&A Ior 6v and 12MHz
Serlal conLrol (SCCn) 8eglsLer
8blL reglsLer used Lo program Lhe sLarL blL sLop blL and daLa blLs of daLa framlng 1CCn* (l1 Auu8LSSALL)
7 6 S 4 3 2 1 0
SM0 SM1 SM 8Ln 18 88 1l 8l
00 MCuL0
SPll1 8LClS1L8 MCuL
Jl1P llxLu Auu 8A1L
01 MCuL1
8l1 uA81 vA8lALL
Auu 8A1L
10 MCuL
l1 uA81
(MuL1l8CCLSSC8)
llxLu Auu 8A1L
11 MCuL
l1 uA81
(MuL1l8CCLSSC8)
vA8lALL Auu 8A1L
rogrammlng sLeps Lo
Lransfer daLa serlally ( ln
mode 1 )
MuL1l8CCLSSC8
CCMMunlCA1lCn l1
1 CnL? vALlu S1C
l1 CAn CLnL8A1L
ln1L88u1
MM
ln1 CLnL8A1Lu ll
l1 lS 1 nC
ln1L88u1
CLnL8A1Lu lC8
l10
M1
nC ln1L88u1
CLnL8A1Lu unLLSS
vALlu S1C l1
0 MCuL 0
8LCL1lCn
LnALLu l1
1 LnALL
8LCL1lCn
0 ulSALL
8LCL1lCn
xMl1 l1 8
1/0?
8CC8AM
ln MCuL

(MuL1l8CC
LSSC8
MCuL)
8LCLlvL l1 8
x lC8 M0
S1C l1 lC8
M1
l1 8 Cl uA1A
lC8 MCuL

(MuL1l8CCL
SSC8 MCuL)
18nASMl1
ln1L88u1
lLAC
1 Lnu Cl
l1 7 ln M0
Anu
8LG--G CI
S1C l1 ln
C1PL8 MCuL
0 CLLA8Lu
? 8CC8AM
A1 lS8
8LCLlvL
ln1L88u1
lLAC
1 Lnu Cl
l1 7 ln M0
Anu nI
W
@nCDGn
S1C l1 ln
C1PL8 MCuL
0 CLLA8Lu
? 8CC8AM
A1 lS8
12/12/2011 BE V (ELECTRCAL) ADVED 2010
SM2 : used for muIti processor communication - make it 0 for mode 0
REN : receive enabIe (by software enabIe/disabIe)
when high, it aIIows the 8051 to receive data on the RXD pin of the 8051
8051 in simuItaneous transmit and receive mode REN must be set to 1
REN = 0 means receiver is disabIed
TB8 : transmit bit8 - not wideIy used - make it 0 - used for seriaI mode 2 and 3
RB8 : receive bit 8- not wideIy used - make it 0 - in mode 1 this bit gets a copy of
the stop bit, when 8 bit data is received . AIso used for mode 2 and 3.
TI : transmit interrupt fIag set by H/W after send , cIear by SW
when 8051 finishes the transfer of the 8 - bit character, it raises the TI fIag to
indicate that it is ready to transfer another byte. TI is raised at the beginning
of the stop bit.
RI : receive interrupt fIag set by HW after received ,cIear by SW
when 8051 receives data seriaIIy via RXD it gets rid of the start and stop bit
and pIaces the byte in SBUF register. Then it raises the RI bit to indicate that
the byte has been received and shouId be picked up before it is Iost. RI is
raised haIfway through the stop bit.
RI =0, NEXT BYTE CAN BE TRANSFERRED TO SBUF. FAILING TO MAKE RI =0, NEXT BYTE
WILL BE LOST.
IF DATA IS READ BEFORE RI =1, GARBAGE DATA READ,
W SL8lAL uA1A ln1L88u1
W SLCJ 8CCLSS MAn? ms/byLe
W Sr daLa flags ln scon saves Llme
W 1x under program conLrol 8x random and unpredlcLable
W rogram musL read 8l/1l whenever serlal lnLerrupL ls acLlvaLe
W uA1A 18AnSMlSSlCn
W SLarLs when daLa wrlLLen ln Sul
W Jhen all blLs are Lransferred Sul ls empLy and 1l 1
W Jhen 1l1 anoLher daLa can be loaded ln Sul (JPA1 ll nC1 JAl1Lu lC8 1l 1?)
W uA1A 8LCL1lCn
W 8Ln 1(SCCn4)
W MCuL 0 8l 0 Jhen daLa recelved 8l 1 prog reads Sul and clears 8l
W M1 8l 1 uaLa recepLlon over and daLa may be read ln 8l 0 before lasL blL ls recelved
oLherwlse lncomlng daLa wlll be losL
W lncomlng daLa Lransferred Lo Sul only afLer lasL blL of daLa ls recelved revlous daLa can be
read from Sul whlle new daLa ls recelved
RI
1I
SLRIAL IN1R ,0023h,
16
Mode 0 of operaLlon
W Mode 0 slmply a shlfL reglsLer
Serlal daLa enLers and exlLs
Lhrough 8xu
1xu ouLpuLs Lhe shlfL clock
8 blLs are LransmlLLed/recelved
(LS flrsL)
1he baud raLe ls flxed aL 1/1
Lhe osclllaLor frequency
W AppllcaLlon
orL expanslon
Mode 0 of operaLlon
W As can be seen in the diagram the terms TXD and RXD are
misleading in mode 0.
W TXD serves as the clock while RXD is used Ior both receiving
and transmitting data.
W In mode 0, the serial port is only halI duplex; it cannot transmit
and receive data at the same time because the same line (RXD)
is being used Ior both transmit and receive.
W The serial port in mode 0 is an example oI synchronous
communic,tion; the clock signal is sent with the data on the
TXD line. TXD pulses at the same Irequency as the machine
cycle means TXD runs at 1/12th the Irequency oI the system
clock.
W II we are using a 12MHz system clock, then the Irequency oI
TXD is 1MHz, which implies its cycle length is 1us.
ThereIore, each bit is active on the RXD line Ior 1us. To shiIt
the entire 8-bit word along RXD takes 8us.
ode I of operofion
W Mode 1
Ten bits are transmitted (through TxD) or received (through RxD)
(A start bit (0), 8 data bits (LS Iirst), and a stop bit (1) )
On receive, the stop bit goes into R8 in SCON
the baud rate is determined by the Timer 1 overIlow rate.
Timer1 clock is 1/32 machine cycle (MC1/12 XTAL)
1imer clock can be programmed as 1,16 o machine cycle
1ransmission is initiated by any instruction that uses SBUl as a destination
register.
Sett|ng the Ser|a| ort 8aud ate
W serial ports baud rate setting is required Ior modes 1 and 3.
W The aud Rate is determined based on the oscillators Irequency when
in mode 0 and 2.
W In mode 0, the baud rate is always the oscillator Irequency divided by
12. This means iI youre crystal is 11.059Mhz, mode 0 baud rate will
always be 921,583 baud.
W In mode 2 the baud rate is always the oscillator Irequency divided by
64, so a 11.059Mhz crystal speed will yield a baud rate oI 172,797.
baud rate can also be doubled by smod 1
W In modes 1 and 3, the baud rate is determined by how Irequently timer
1 overIlows.
W The more Irequently timer 1 overIlows, the higher the baud rate. There
are many ways one can cause timer 1 to overIlow at a rate that
determines a baud rate, but the most common method is to put timer 1
in 8-bit auto-reload mode (timer mode 2) and set a reload value (TH1)
that causes Timer 1 to overIlow at a Irequency appropriate to generate
a baud rate.
Sett|ng the Ser|a| ort 8aud ate
W To determine the value that must be placed in TH1 to generate a given baud
rate, we may use the Iollowing equation (assuming PCON.7 (SMOD) is
clear). Load TMOD with 0010 0000 20H timer1 in autoreload mode(m2)
W TH1 256 ((2
SMOD
/32)* (I
Crystal
/ 12)) / aud)
W TH1 256 - ((I
Crystal
/ 384) / aud)
W TH1 256 - ((I
Crystal
/ 384) / aud)
TH1 256 - ((11059200 / 384) / 9600 )
TH1 256 - ((28,800) / 9600)
TH1 256 3 253 FD H
1
rogramm|ng steps to transfer data ser|a||y
( |n mode 1 )
1. TMOD Reg is loaded with 20H (timer 1 in mode 2) to set the baud
rate
2. TH1 is loaded with the count Ior speciIic baud rate
3. SCON with 50H iI simultaneous transmit and receive operations are
required else only Ior transmit load 40 H Ior mode 1.
4. Tr1 is set to start time -1
5. TI is cleared by CLR TI means make it 0 during the starting
6. The character byte to be transIerred serially is written into S&F.
7. TI Ilag is to be monitored to iI the character has been transIerred
completely.
8. To transIer the next character go to step 5Serial control (SCON)
Register 8-bit register used to pro...
9. TMOD
W JrlLe a program for Lhe 8031 Lo Lransfer leLLer
A" serlally aL 4800 baud conLlnuously
W So|ut|on
MCv 1MCu#0P Llmer 1mode (auLo
reload)
MCv 1P1#6 4800 baud raLe
MCv SCCn#30P 8blL 1 sLop 8Ln enabled
SL1 181 sLarL Llmer 1
ACAln MCv Sul#"A" leLLer A" Lo Lransfer
PL8L !n 1lPL8L walL for Lhe lasL blL
CL8 1l clear 1l for nexL char
S!M ACAln keep sendlng A
W JrlLe a C program for 8031 Lo Lransfer Lhe leLLer A" serlally aL 4800
baud conLlnuously use 8blL daLa and 1 sLop blL
W So|ut|on
#lnclude reg31h
vold maln(vold)
1MCu0x0 //use 1lmer 1 mode

1P10xlA //4800 baud raLe
SCCn0x30
1811
whlle (1)
Sul'A' //place value ln buffer

whlle (1l0)
1l0

W JrlLe a program for Lhe 8031 Lo Lransfer 8characLers sLored aL 0h Lo 7h serlally aL 600
baud 8blL daLa 1 sLop blL do Lhls conLlnuously
W So|ut|on
MCv 1MCu#0P Llmer 1mode (auLo reload)
MCv 1P1# 600 baud raLe
Mov r0 #0h u1 Cln1L8 A1 0P
MCv 81 #08
ACAln MCv A [80 18AnSlL8 ?1L
ACALL 18AnS
lnC 80
u!nZ 81 ACAln
ACAln1 S!M ACAln1 keep dolng lL
serlal daLa Lransfer subrouLlne
18AnS MCv SulA load Sul
PL8L !n 1lPL8L walL for Lhe lasL blL
CL8 1l geL ready for nexL byLe
8L1
W JrlLe an 8031 C program Lo Lransfer Lhe message ?LS" serlally aL 600 baud 8blL daLa 1 sLop blL
uo Lhls conLlnuously
W So|ut|on
#lnclude reg31h
vold Ser1x(unslgned char)
vold maln(vold)

1P10xlu //600 baud raLe
SCCn0x30
1811 //sLarL Llmer
whlle (1)
Ser1x('?')
Ser1x('L')
Ser1x('S')
vold Ser1x(unslgned char x)
Sulx //place value ln buffer

whlle (1l0) //walL unLll LransmlLLed
1l0

rogramm|ng steps to rece|ve data ser|a||y
( |n mode 1 )
1. TMOD Reg is loaded with 20H (timer 1 in mode 2) to set the baud
rate
2. TH1 is loaded with the count Ior speciIic baud rate
3. SCON with 50H in mode 1, receive enable must be turned on
4. Tr1 is set to start time -1
5. RI is cleared by CLR RI means make it 0 during the starting
6. The character byte to be transIerred serially is written into S&F.
7. RI Ilag is to be monitored to iI the character has been transIerred
completely.
8. To transIer the next character go to step 5
W JrlLe a program for Lhe 8031 Lo recelve byLes of daLa serlally and
W puL Lhem ln 1 seL Lhe baud raLe aL 4800 8blL daLa and 1 sLop blL
So|ut|on
MCv 1MCu#0P Llmer 1mode (auLo reload)
MCv 1P1#6 4800 baud raLe
PL8L !n 8lPL8L walL for char Lo come ln
MCv ASul savlng lncomlng byLe ln A
MCv 1A send Lo porL 1
CL8 8l geL ready Lo recelve nexL byLe
S!M PL8L keep geLLlng daLa
W rogram Lhe 8031 ln C Lo recelve byLes of daLa serlally and puL
Lhem
ln 1 SeL Lhe baud raLe aL 4800 8blL daLa and 1 sLop blL
W So|ut|on
#lnclude reg31h
vold maln(vold)
unslgned char mybyLe

1P10xlA //4800 baud raLe
SCCn0x30
1811 //sLarL Llmer
whlle (1)
//repeaL forever
whlle (8l0) //walL Lo recelve
mybyLeSul //save value
1mybyLe //wrlLe value Lo porL
8l0

#lnclude reg31h
vold uarL_seLup()
1MCu 0x0 // conflgure Llmer1 for Mode operaLlon for Lhe correcL baud raLe
1P1 0xlu // 600 bps for 1103 MPz clock
1CCn 0x40 // SLarL Llmer 1 by seLLlng 181 1
SCCn 0x30 // SeL Serlal lC Lo recelve and normal mode
8l0 //8ecelve lnLerrupL llag ls cleared
1l0 //1x lnLerrupL flag ls cleared
unslgned char 8xuaLa()
unslgned char rcv_daLa

rcv_daLa Sul //lf any daLa ls avallable copy lL from Sul
reLurn rcv_daLa //reLurn Lhe recelved daLa
vold 1xuaLa(unslgned char Lx_daLa)
Sul Lx_daLa //1ransmlL daLa LhaL ls passed Lo Lhls funcLlon

whlle(1l 0) //walL whlle daLa ls belng
LransmlLLed

vold maln(vold)
unslgned char rx_daLaLx_daLa

uarL_seLup() // calllng Lhe uA81 seLup funcLlon
whlle(1) //loop conLlnuously
lf (8l1) // lf any daLa ls presenL sLore lL and LransmlL lL back
rx_daLa 8xuaLa() //geL Lhe recelved daLa

Lx_daLa rx_daLa
1xuaLa(Lx_daLa) // LransmlL lL back Lo Lhe C 1hls daLa can be vlewed onLo Lhe Lermlnal
8l 0 //Clear recelve lnLerrupL MusL be cleared by Lhe user
1l 0 b//Clear LransmlL lnLerrupL MusL be cleared by Lhe user

JrlLe an 8031 C rogram Lo send Lhe Lwo messages normal Speed"
and Plgh Speed" Lo Lhe serlal porL Assumlng LhaL SJ ls connecLed
Lo pln 0 monlLor lLs sLaLus and seL Lhe baud raLe as follows
SJ 0 8800 baud raLe
SJ 1 36k baud raLe
Assume LhaL x1AL 1103 MPz for boLh cases
W So|ut|on
#lnclude reg31h
sblL M?SJ0 //lnpuL swlLch
vold maln(vold)
unslgned char z
unslgned char Mess1normal Speed"
unslgned char MessPlgh Speed"
1P10xll //8800 for normal
SCCn0x30
1811 //sLarL Llmer
lf(M?SJ0)
for (z0z1z++)
SulMess1z //place value ln buffer

whlle(1l0) //walL for LransmlL
1l0
else
CCnCCn|0x80 //for hlgh speed of 36k

for (z0z10z++)
SulMessz //place value ln buffer

whlle(1l0) //walL for LransmlL
1l0

CperaLlon ln MulLlprocessor mode
W 8031 operaLes ln mulLlprocessor mode for serlal communlcaLlon Mode and
Mode ln mulLlprocessor mode a MasLer processor can communlcaLe wlLh more
Lhan one slave processors 1he connecLlon dlagram of processors communlcaLlng
ln MulLlprocessor mode ls glven
W 1he MasLer communlcaLes wlLh one slave aL a Llme 11 blLs are LransmlLLed by Lhe
MasLer vlz Cne sLarL blL (usually 0) 8 daLa blLs (LS flrsL) 18 and a sLop blL
(usually 1) 18 ls 1 for an address byLe and 0 for a daLa byLe
W lf Lhe MasLer wanLs Lo communlcaLe wlLh cerLaln slave lL flrsL sends Lhe address of
Lhe slave wlLh 181 1hls address ls recelved by all Lhe slaves Slaves lnlLlally have
Lhelr SM blL seL Lo 1 All slaves check Lhls address and Lhe slave who ls belng
addressed responds by clearlng lLs SM blL Lo 0 so LhaL Lhe daLa byLes can be
recelved
W lL should be noLed LhaL ln Mode recelve lnLerrupL flag 8l ls seL lf 8Ln1 8l0
and Lhe followlng condlLlon ls Lrue
W SM1 and 881 and a valld sLop blL ls recelved Cr
W SM0 and a valld sLop blL ls recelved
W AfLer Lhe communlcaLlon beLween Lhe MasLer and a slave has been esLabllshed
Lhe daLa byLes are senL by Lhe MasLer wlLh 180 Pence oLher slaves do noL
respond /geL lnLerrupLed by Lhls daLa as Lhelr SM ls pulled hlgh (1)
18
Mode of operaLlon
W Mode 2 :
Eleven bits are transmitted (through TxD), received (through RxD)
W A start bit (0)
W 8 data bits (LS Iirst)
W A programmable 9th data bit
W and a stop bit (1)
On transmit, the 9th bit (T8) can be assigned 0 or 1.
On receive, the 9the data bit goes into R8 in SCON.
the 9
th
can be parity bit
The baud rate is programmable to 1/32 or 1/64 the oscillator Irequency in Mode
2 by SMOD bit in PCON register
W Mode 3
Same as mode 2
ut may have a variable baud rate generated Irom Timer 1.
W Modes 1 and 3 can be used Ior standard
asynchronous communication.
W In this case, the RXD and TXD bits are
normally routed through a level converter chip
to produce and receive the speciIied RS232
levels.
W Modes 2 and 3 can be used Ior multiprocessor
communication. In this case, the 9th bit can be
used as an address marker (bit 9 1).
W When the master sends out an address byte, all
slaves will receive the byte and only one will be
identiIied as the target Ior the message.
W That processor will clear its SM2 bit and will be
interrupted Ior all Iurther message bytes.
W Other slaves will leave their SM2 bit set and
will not be interrupted by the data bytes that
Iollow.
Mode of operaLlon
JhaL ls SMCu
it 7 oI PCON register
II SMOD1 double baud rate
PCON is not bit addressable
How to set SMOD
ov , pcon
Setb ,cc.7
ov pcon,
ln1L88u1
W MASkALL (?) nCnMASkALL
W vLC1C8Lu (?) nCn vLC1C8Lu
W Ldge Lrlggered or level Lrlggered
W CPLCk CCnul1lCn
W S/J (CLLlnC) P/J CALLS(ln1L88u1)
W lLAC/ln CPLCku 8LLA1LuL? ? S/J lLAC/ln CPLCkLu ? P/J
W !uM ll CCnul1lCn CALL lS8
W 1AkLS M 1lML 1C CPLCk LxLCu1L 1AkLS M 1lML 1C LxLCu1L (MuS1 lC8
W 81 ALlCA1lCnS)
W Many devlces cannoL be checked many devlces can be checked
W rlorlLy cannoL be asslgned prlorlLles can be asslgned
W ln1L88u1 CLnL8A1lCn
1 ln1L8nAL CPl CL8A1lCn Lx1L8nAL SCu8CL
10 11 SCCM (8l/1l) ln10 ln11 reseL
19
IN1LRRU!1 UNDLR CON1ROL Ol !ROGRAM
1. IL ,BLOCK ALL OR COMBINA1ION IN1R,
2. I! ,ClANGL !RIORI1\ LLVLL,
By deault leel triggered, leel has to be remoed or same src will interrupt
ln1L88u1 8L1u8n
MCA ADVLD BLVI,LLLC1RICAL,
W ln18 PJ CALL
lL0 000P 10 000P
lL1 001P 11 001P
SCCM 00P
W 8L1l
C CP
C CL
LnALL ln18 LCClC
W ALL Sl8(lnCLuulnC SJ)/8LC uSLu ? lS8 JlLL L CPAnCLu CCn1Lx1
SAvlnC lS nLCLSSA8?
W ln18 CAn L LnALLu/ ulSALLu ? lL 8LC
W 8lC8l1? CAn L CPAnCLu l8CM uLlAuL1 ? l 8LC
lOR IN1R !RODUCLD B\ 10 &11, 1l0 & 1l1 RLSL1S AU1OMA1ICALL\ A1 ISR
RI,1I !RODUCLS SR IN1R. RI,1I NLLDS 1O BL CLLARLD B\ !ROG A1 ISR
lOR IN10,IN11
lLAGS ,IL0,IL1 IN 1CON, - RLSL1S AU1OMA1ICALL\ A1 ISR lOR LDGL 1RIGGLRLD IN1R
- RLSL1 B\ !ROGRAM A1 ISR lOR LO\ LLVLL 1RIGGLRLD IN1R
- MUS1 RLMOVL LO\ LLVLL BLlORL RL1I,LLSL SAML IN1R
!C -S1ACK
IN1R DISABLLD
lLI!lLO! 1,
S1ACK -!C
IN1R DISABLLD lLI!lLO! 0
MAIN !ROG
IN1R ISR
LJM!
SR...
.....
.....
IRL1
nC C1PL8 ln18 Cl
SAML/LCJL8
8lC8l1? ALLCJu
W lnLerrupL flags sampled aL S3 of every lnsLrucLlon cycle (1 lnLsL cycle x machlne
cycle)
W lf one of Lhe flags was seL aL S3 of Lhe precedlng lnsLrucLlon cycle Lhe polllng deLecLs
lL and Lhe lnLerrupL process generaLes a long call (LCALL) Lo Lhe approprlaLe vecLor
locaLlon of Lhe lnLerrupL
W 1he LCALL ls generaLed provlded Lhls hardware generaLed LCALL ls noL blocked by any
one of Lhe followlng condlLlons
1 An lnLerrupL of equal or hlgher prlorlLy level ls already ln progress
1he currenL polllng cycle ls noL Lhe flnal cycle ln Lhe execuLlon of Lhe lnsLrucLlon ln
progress
1he lnsLrucLlon ln progress ls 8L1l or any wrlLe Lo lL or l reglsLers
W Jhen an lnLerrupL comes and Lhe program ls dlrecLed Lo Lhe lnLerrupL vecLor address
Lhe rogram CounLer (C) value of Lhe lnLerrupLed program ls sLored (pushed) on Lhe
sLack 1he requlred lnLerrupL Servlce 8ouLlne (lS8) ls execuLed AL Lhe end of Lhe lS8
Lhe lnsLrucLlon 8L1l reLurns Lhe value of Lhe C from Lhe sLack and Lhe orlglnally
lnLerrupLed program ls resumed
8LSL1
W nMl
W C nC1 S1C8Lu Cn S1ACk
W Ln1L8 ln 8LSL1 S1A1L ll 8LSL1 ln 1
W Al1L8 8LSL1
SofLware generaLed lnLerrupL
W rogrammer can generaLe sofLware lnLerrupL
by seLLlng blLs 8l/1l ln SCCn or
lL0/lL1/1l0/1l1 ln 1CCn
no asslgnmenL for c
W Assume LhaL lnL1 ls connecLed Lo swlLch whlch ls normally hlgh whenever lL goes low lL Lurns on
LLu connecLed Lo 1 whlch ls normally offLLu should be on Llll Lhe Llme swlLch ls low LLu should
be on momenLarlly
W level Lrlggered lnLerrupL
W org 0000h
W l[mp maln lsr for lnL1 aL 001h Lake [ump above LhaL address
W
W org 001h lsr for lnL1
W seLb p1 led on
W mov r #0ffh
W here mov r #0ffh delay rouLlne
W here1 d[nz r here1
W d[nz r here
W clr p1 led off
W reLl
W
W org 000h
W maln mov le #84h ea 1 lnL11 by defaulL lnL1 ls level Lrlggered
W
W clr p1
W here s[mp here
W end
W Assume LhaL lnL1 ls connecLed Lo swlLch whlch ls normally hlgh whenever lL goes low lL Lurns on LLu connecLed Lo
1 whlch ls normally offLLu should be on momenLarlly when key ls pressed
W LuCL Lrlggered lnLerrupL
W org 0000h
W l[mp maln lsr for lnL1 aL 001h Lake [ump above LhaL address
W
W org 001h lsr for lnL1
W seLb p1 led on
W mov r #01h
W here mov r #01h delay rouLlne
W here1 d[nz r here1
W d[nz r here
W clr p1 led off
W reLl
W
W org 000h
W maln mov le #84h ea 1 lnL11 by defaulL lnL1 ls level Lrlggered
W seLb Lcon lnL1 becomes edge Lrlggered
W clr p1
W here s[mp here
W end
W
W Lxample program Lo generaLe a 30Pz square wave aL 17 uslng 1lmer/counLer 1 ln
16blL mode ln1L88u1 drlven
C8C 0000h enLry address for 8031 8LSL1
L!M MAln MAln sLarLs beyond lnLerrupL vecLor space
C8C 001h vecLor address for lnLerrupL
L!M lS8_1lML81 [ump Lo sLarL of lS8_1lML81
C8C 0100h enLry address for maln
MAln
MCv 1MCu #00010000b 1lmer 1 ls seL for mode 1 1lML8 operaLlon
MCv 1P1 #0u8h 1lmer 1 hlgh byLe ls loaded
MCv 1L1 #0l0h 1lmer 1 low byLe ls loaded
MCv lL #10001000b enable 1lmer 1 lnLerrupL
SL1 181 sLarL 1lmer 1
LCC L!M LCC [usL loop around dolng noLhlng
lS8_1lML81
CL8 181 sLop 1lmer 1
MCv 1P1 #0u8h reloads 1lmer 1 values ln 1P1
MCv 1L1 #0l0h and ln 1L1
CL 17 complemenL 1 blL 7
SL1 181 sLarL 1lmer 1
8L1l reLurn from lnLerrupL
Lnu
JrlLe a program uslng lnLerrupLs Lo do Lhe followlng (a) 8ecelve daLa serlally and senL lL Lo 0
(b) Pave 1 porL read and LransmlLLed serlally and a copy glven Lo (c) Make Llmer 0 generaLe
a square wave of 3kPz frequency on 01 Assume LhaL x1AL1103 SeL Lhe baud raLe aL
4800
C8C 0
L!M MAln
C8C 000P lS8 for Llmer 0
CL 01 Loggle 01
8L1l reLurn from lS8
C8C P
L!M SL8lAL [ump Lo serlal lnLerrupL lS8
C8C 0P
MAln MCv 1#0llP make 1 an lnpuL porL
MCv 1MCu#PLlmer 1mode (auLo reload)
MCv 1P1#0l6P4800 baud raLe
MCv SCCn#30P8blL 1 sLop ren enabled
MCv 1P0# for 3kPZ wave
#lncludereg31h
#deflne L0lsb 0x0b
#deflne L0msb 0xc
30nsec
sblL C 10
sblL wlk 1
sblL ? 11
sblL nwlk 14
sblL 8 1
unslgned counL0
vold L0lsr(vold)
vold maln()
10
1MCu 0x01
1L0 L0lsb
1P0 L0msb
LA 1
L10 1
1801
C 1
wlk 1
? 0
8 0
nwlk 0
whlle(1)

oid t0isr,oid, interrupt 1
1L0 t0lsb,
1l0 t0msb,
count--,
i,count00,
G 0,
wlk 0,
\ 1,
nwlk 1,
}
i,count500,
\ 0,
R 1,
}
i,count2000,
R 0,
nwlk 0,
G1,
wlk1,
count0,
}

Adv Pres SR Comm

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Adv Pres SR Comm

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8031 MlC8CCCn18CLLL8S

1MCu0x0 //use 1lmer 1 mode

Sul'A' //place value ln buffer

12,12,2011 BL VI ,LLLC1RICAL, ADVLD 2010

1MCu0x0 //use 1lmer 1 mode

vold Ser1x(unslgned char x)

Sulx //place value ln buffer

12,12,2011 BL VI ,LLLC1RICAL, ADVLD 2010

unslgned char mybyLe

12,12,2011 BL VI ,LLLC1RICAL, ADVLD 2010

unslgned char 8xuaLa()

unslgned char rcv_daLa

vold 1xuaLa(unslgned char Lx_daLa)

Sul Lx_daLa //1ransmlL daLa LhaL ls passed Lo Lhls funcLlon

12,12,2011 BL VI ,LLLC1RICAL, ADVLD 2010

unslgned char rx_daLaLx_daLa

lf (8l1) // lf any daLa ls presenL sLore lL and LransmlL lL back

rx_daLa 8xuaLa() //geL Lhe recelved daLa

12,12,2011 BL VI ,LLLC1RICAL, ADVLD 2010

SulMess1z //place value ln buffer

CCnCCn|0x80 //for hlgh speed of 36k

SulMessz //place value ln buffer

12,12,2011 BL VI ,LLLC1RICAL, ADVLD 2010

12,12,2011 BL VI ,LLLC1RICAL, ADVLD 2010

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