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EVOLUTION OF CISC AND RISC CONCEPTS RISC VS CISC INTRODUCTION TO ARM PROCESSOR FAMILY OF ARM BLOCK DIAGRAM OF ARM REGISTERS DIAGRAM 3 STAGE PIPELINED ARM 5 STAGE PIPELINED ARM INSTRUCTION SETS OF ARM
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Out lines
cisc evolution
COMPILER TARGET
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COMPIL ER
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THE
AIM OF PROCESSOR DESIGN SHOULD DEFINE HIS OR HER INSRTN SET TO BE GOOD COMPILER TARGET
COMPILER TARGET ??
COMPLEXITY
MAIN MEMORY CONTROLLED BY MICRO CODE ROMS WHICH ARE FASTER THAN MAIN MEMORY
MINI COMPUTERS USES CISC IN 1970, MICRO PROCESSORS DEVEL0PED
FASTLY IN SEMICONDUCTOR INDUSTRY BUT MICRO CODE ROM IS NEEDED FOR ALL COMPLEX ROUTINES
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WHAT IS CISC ??
CISC is an acronym for Complex Instruction Set
Computer and are chips that are easy to program and which make efficient use of memory. Since the earliest machines were programmed in assembly language and memory was slow and expensive,
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RISC evolution
INSTRN TYPE
DATA MOVEMENT CONTROL FLOW ARITHMETIC OPERATION COMPARISIONS LOGICAL OPERATIONS `OTHERS
DYNAMIC USAGE IN %
43 23 15 13
5 1
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WHAT IS RISC ??
RISC, or Reduced Instruction Set Computer. is a
type of microprocessor architecture that utilizes a small, highly-optimized set of instructions, rather than a more specialized set of instructions often found in other types of architectures.
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RISC VS CISC
CISC
Complex instructions taking multiple cycles. reference memory.
3 Highly pipelined
5 Fixed format
instructions.
32 BIT
LOAD STORE ARCHITECTURE FEWER ADDRESSING MODES INSTRUCTION PIPELINE LARGE NUMBER OF REGISTERS DELAYED LOADS AND BRACHES SEPARATE INSTRN AND DATA
STREAMS
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EVOLUTION OF ARM
Founded in 1990. ARM -Advanced Risc
Machines
ARM Holdings.
ARM Holding is a joint
features
Features used Features rejected Load - strore Register architecture window Fixed length 32 bit instructions 3 address Delayed branches Single 5/6/12 cycle
cont
The combination of the simple hardware with
an instruction set that is grounded in risc ideas but retains a few key cisc features
instructions) available)
37 pieces of 32-bit integer registers (16 Pipelined (ARM7: 3 stages) Cached (depending on the
implementation)
Von Neuman-type bus structure (ARM7),
Harvard (ARM9)
8 / 16 / 32 -bit data types
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family of arm
ARM REVISION ARM V 1 ARM V2 ARM V 2a ARM V 3 ARM V 3M ARM V4 ARM V 4T ARM V5 TE ARM V STEJ ARM V6 PROSCESSORS CORE ARM 1 ARM 2 ARM 3 ARM 6 and ARM 7DI ARM 7M STORNG ARM ARM 7 TDMI and ARM 9T ARM 9E and ARM 10 E ARM 7EJ and ARM 926EJ ARM 11
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NOMENCLATURE
ARM
{X}{Y}{Z}{T}{D}{M}{I}{E}{J}{F}{S}
T: Thumb D: On-chip debug ARM support M: Enhanced multiplier TDM7I I: Embedded ICE hardware T2: Thumb-2 S: Synthesizable code E: Enhanced DSP instruction
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CD CD
DATA
SIGN EXTEND WRI ED TE READ REGISTER FILES R0 R15 BARREL SHIFTER ALU ADDRESS REGISTER ADDRESS
INSTRN DECODER Rd
MAC
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3 STAGE PIPELINING
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REGISTERS OF ARM
ARM7 register set
thirty-seven 32bit registers. 30 are general purpose registers 16 general purpose registers(R0 to R15)
Register structure depends on mode of operation R13 - Stack Pointer (SP) R14 - subroutine Link Register for branch and link instructions 5/6/12
IRQ
SVC
Undef
spsr
spsr
spsr
spsr
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processor,processor operation mode,interrupt B3enable bit B28 B2 B25 to B24B8 B7 B6 B5 B0 B30 B29 status,etc.
1 7 B26 to B23 to B4
V Q
F T Mod
e Sele ct
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OPERATING MODES
1.
User Mode- Normal program execution state high priority interrupt is raised.
2. Fast Interrupt Processing (FIQ) Mode - when a 3. Normal Interrupt Processing (IRQ) Mode4.
when a normal priority interrupt is raised. Supervisor /Software Interrupt ModeProtected mode for operating system support . Eg: when reset /software interrupt instruction is executed. aborted.
7 MODES
User
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr spsr spsr spsr spsr spsr
FIQ
User mode r0-r7, r15, and cpsr
IRQ
User mode r0-r12, r15, and cpsr
SVC
User mode r0-r12, r15, and cpsr
Undef
User mode r0-r12, r15, and cpsr
Abort
User mode r0-r12, r15, and cpsr
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BARALLEL SHIFTER
LSL : Logical Left Shift
C F
Destination
Destination
Multiplication by a power of 2
Destination
C F
C F
C F
Division by a power of 2
Bit rotate with wrap around RRX: Rotate Right Extended from LSB to MSB C Destination
F
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BARREL SHIFTER
Operand 1 Operand 2
Barrel Shifter
be:
5 bit unsigned integer Specified in bottom byte of
another register.
constant
Result
Immediate value
8 bit number, with a
processor
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WITH PIPELING
The processor is able to
Clock Cycle
1 2 3
4 5 6 7
3 STAGE PIPELING
FETCH DECOD E FETCH EXECUT E DECOD E FETCH DECODE
EXECUT E
EXECUT E
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program
executed in the
program => compiler dependent CPI: average number of clock cycles per
instructions =>
hazard causes pipeline stalls fclk: frequency
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5 STAGE PIPELING
FETC H DECO DE FETC H EXECU TE DECO DE ACCESS OPERAND EXECU TE WRITE
ACCESS OPERAND
WRITE
FETC H
DECO DE
EXECU TE
ACCESS OPERAND
WRITE
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5 STAGE PIPELING
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32bit
can be considered as a 16bit compressed form of the orginal 32bit ARM instruction. These instructions can be executed by decompressing the instruction to the original 32bit ARM instructions technique that allows Java Bytecode to be executed directly in the ARM architecturea. 5/6/12
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Improved performance from narrow memory Subset of the functionality of the ARM instruction
31
Core has additional most instructions state - by compiler: For execution generated Thumb
Switch between ARM and Thumb using BX
n n n n
1 5
Conditional execution is not used Only Low registers used Constants are of limited size Inline barrel shifter not used
instruction
ADD r2,#1
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ARM10(TDMI) ARM10TDMI processor core: Realizes the ARM instruction set with
Embedded_3_ARM_2003.ppt / 19112002
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ADVANTAGES OF ARM
HIGH CODE DENSITY PRICE SENSITIVE HARD WARE DEBUG TECHNOLOGY SMALL AREA
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APPLICATIONS
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THANK U
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