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A Design Perspective
Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic
Sequential Logic
Inputs COMBINATIONAL LOGIC Current State Registers Q D Next state Outputs
CLK
Naming Conventions
In our text:
a latch is level sensitive a register is edge-triggered
Sequential Circuits
Latches
Positive Latch In D G CLK clk In Out Out stable Out follows In clk In Out Out stable Out follows In Q Out In Negative Latch D G CLK Q Out
Sequential Circuits
LatchLatch-Based Design
N latch is transparent when J = 0
J
N Latch
Logic
P Latch
Logic
Digital Integrated Circuits2nd
Sequential Circuits
Timing Definitions
DATA STABLE tc 2
q
CLK t
DATA STABLE
Sequential Circuits
Characterizing Timing
tD 2 D Q D
Q
Clk
Clk
tC 2
tC 2
Register
Digital Integrated Circuits2nd
Latch
Sequential Circuits
Also: tcdreg + tcdlogic > thold tcd: contamination delay = minimum delay
Sequential Circuits
V o1
1 o V
Vi2
1 o V 5 2 i V
V o2
V o2 = V i 1
V i1 A V i 2 = V o1 1
o V 5 2 i V
B V i 1 = V o2
Sequential Circuits
MetaMeta-Stability
V i 2 5 V o1 V i 2 5 V o1 C A A
V i 1 5 V o2
V i 1 5 V o2
Sequential Circuits
CLK
Q CLK
D CLK
CLK
Sequential Circuits
MuxMux-Based Latches
Negative latch Positive latch (transparent when CLK= 0) (transparent when CLK= 1)
1 D 0
Q D
0 1
CLK
CLK
Q ! Clk Q Clk In
Digital Integrated Circuits2nd
Q ! Clk Q Clk In
Sequential Circuits
MuxMux-Based Latch
CLK
Q CLK D
CLK
Sequential Circuits
MuxMux-Based Latch
CLK
NMOS only
Digital Integrated Circuits2nd
Non-overlapping clocks
Sequential Circuits
Two opposite latches trigger on edge Also called master-slave latch pair
Digital Integrated Circuits2nd Sequential Circuits
MasterMaster-Slave Register
Multiplexer-based latch pair
I2
T2
I3 QM
I5
T4
I6
I1
T1
I4
T3
CLK
Sequential Circuits
ClkClk-Q Delay
2.5
CLK
Volts 1.5 D
tc 2
q(lh)
0.5
tc 2
q(hl)
2 0.5 0
0.5
2.5
Sequential Circuits
Setup Time
3.0 2.5 2.0 Volts 1.5 D 1.0 0.5 0.0 2 0.5 0 0.2 0.4 0.6 time (nsec) 0.8 1 I 2 2 T2 CLK Q QM Volts 3.0 2.5 2.0 1.5 D 1.0 QM 0.5 0.0 2 0.5 0 0.2 0.4 0.6 time (nsec) 0.8 1 CLK I 2 2 T2 Q
Sequential Circuits
T1 CLK
I1 I2
T2 CLK
I3 I4
Sequential Circuits
CLK
CLK
Sequential Circuits
Sequential Circuits
CrossCross-Coupled NAND
Cross-coupled NANDs
S
Added clock
VDD M2 Q M4 Q
CLK
M6
M1
M3
M8
CLK
M5
M7
This is not used in datapaths any more, but is a basic building memory cell
Digital Integrated Circuits2nd Sequential Circuits
Sizing Issues
2.0 3 Q 1.5 Q (Volts) 2 1.0 Volts S W = 0.5 Q m W = 0.6 Q m W = 0.7 Q m 1 0.5 W = 1Q m 0.0 2.0 2.5 3.0 W/L 5 and 6 (a) 3.5 4.0 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 time (ns) (b) W = 0.8 Q m W = 0.9 Q m
Transient response
Sequential Circuits
Storage Mechanisms
Static Dynamic (charge-based)
CLK
CLK
Q CLK
CLK
D
CLK
Sequential Circuits
CLK
Sequential Circuits
1.05tC 2
tC 2
tSu tH (b)
tD 2
Sequential Circuits
D
Inv1
D1
SM
QM
Clk-Q Delay
CP
TClk-Q TSetup-1
Time
Data TSetup-1
t=0
Clock
Time
Sequential Circuits
D
Inv1
D1
SM
QM
Clk-Q Delay
CP
TClk-Q
TSetup-1
Time
Data TSetup-1
t=0
Clock
Time
Sequential Circuits
D
Inv1
D1
SM
QM
Clk-Q Delay
CP
TClk-Q TSetup-1
Time
Data TSetup-1
t=0
Clock
Time
Sequential Circuits
D
Inv1
D1
SM
QM
Clk-Q Delay
TClk-Q
CP
TSetup-1
Time
Data TSetup-1
t=0
Clock
Time
Sequential Circuits
D
Inv1
D1
SM
QM
CP
TSetup-1
Time
Data
Clock TSetup-1
t=0 Time
Sequential Circuits
D
Inv1
D1
SM
QM
CP
0
TClk-Q THold-1
Time
Clock THold-1
t=0
Data
Time
Sequential Circuits
D
Inv1
D1
SM
QM
CP
0
TClk-Q THold-1
Time
Clock THold-1
t=0
Data
Time
Sequential Circuits
D
Inv1
D1
SM
QM
CP
0
TClk-Q
THold-1
Time
Clock
Data THold-1
t=0 Time
Sequential Circuits
D
Inv1
D1
SM
QM
TClk-Q
CP
THold-1
Time
Clock THold-1
t=0
Data
Time
Sequential Circuits
D
Inv1
D1
SM
QM
TClk-Q
CP
THold-1
Time
Clock
Data THold-1
t=0 Time
Sequential Circuits
Other Latches/Registers:
VDD M2 VDD M6
2MOS C
CLK D CLK
M4 X M3 CL1
CLK
M8 Q CL2
CLK
M7
M1
M5
Master Stage
Slave Stage
Sequential Circuits
Pipelining
REG a
a REG REG REG
REG
REG CLK
CLK REG b
log
Out
b
CLK REG
log
Out
CLK
CLK
CLK
CLK
CLK
Reference
Pipelined
Sequential Circuits
Positive latch Negative latch (transparent when CLK= 1) (transparent when CLK= 0)
Digital Integrated Circuits2nd Sequential Circuits
PDN
In1
In2
AND latch
Sequential Circuits
TSPC Register
VDD CLK VDD VDD Q Q CLK M8
M3
M6 Y
M9
CLK
M2
M5
M1
CLK
M4
M7
Sequential Circuits
Pulse-Triggered Latch L2
D Q Clk Data Clk
L
D Q Clk
Sequential Circuits
Pulsed Latches
VDD VDD M3 M6 CLK Q D CLKG M2 CLKG M5 MP X CLKG VDD
M1
M4
MN
(a) register
Sequential Circuits
Pulsed Latches
Hybrid Latch Flip-flop (HLFF), AMD K-6 and K-7 :
CLK P1 P3 M6 P2 M5 M4
M3 D M2 M1
CLKD
Sequential Circuits
Hybrid Latch-FF Timing Latch3.0 2.5 2.0 Volts 1.5 1.0 0.5 0.0 20.5 0.0
Digital Integrated Circuits2nd
CLK
CLKD
0.2
0.8
1.0
Sequential Circuits
LatchLatch-Based Pipeline
CLK CLK CLK
In C1
F C2
G C3
Out
CLK CLK
Compute F
compute G
Sequential Circuits
V OH
V OL
VM
Digital Integrated Circuits2nd
VM +
Vi n
Sequential Circuits
VM
t0
t0 + tp
Sequential Circuits
M2 Vin X
M4 Vout
M1
M3
Moves switching threshold of the first inverter Digital Integrated Circuits2nd Sequential Circuits
(V) 1.0 X V
0.5 0.0 0.0
VM2
(V) x1.0 V
0.5 0.0 0.0
k=1 k=3 k=2 k=4 0.5 1.0 1.5 Vin (V) 2.0 2.5
0.5
2.0
2.5
The effect of varying the ratio of the PMOS device M4. The width is k* 0.5M m.
Sequential Circuits
Sequential Circuits
Multivibrator Circuits
R S Bistable Multivibrator flip-flop, Schmitt Trigger
Sequential Circuits
TransitionTransition-Triggered Monostable
In
DELAY td
Out td
Sequential Circuits
In
VM
(b) Waveforms.
Out t1 t2
Sequential Circuits
Ring Oscillator
3.0 2.5 2.0 Volts 1.5 1.0 0.5 0.0 20.5 0.0 0.5 time (ns) 1.0 1.5 V1 V3 V5
Sequential Circuits
Relaxation Oscillator
Out1 I1 I2 Out2
R Int
T = 2 (log3) RC
Digital Integrated Circuits2nd
Sequential Circuits
VDD
M4
M2
In
M1
Iref Vcontr
M3 M5
Iref
6 t pH L (nsec) 4 2
0.0 0.5
2.5
Sequential Circuits
v3
V ctrl
delay cell
3.0 2.5 2.0 1.5 1.0 0.5 0.0 2 0.5 0.5 1.5 time (ns) 2.5 3.5 V1 V2 V3 V4
Sequential Circuits