AT91 Microcontroller

AT91RM9200DK/SAM9261 FAQ What to check for in Your own design!

By Ulf Samuelsson Atmel Nordic AB

April 2005 v1.0

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AT91RM9200DK
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Early Development Kit for the AT91RM9200 Now replaced by the AT91RM9200EK Main differences
- Less interfaces - No buffering

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Designs based on the AT91RM9200DK

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JTAG Reset Enabling Buffers on Databus CompactFlash Interface SSC incompatability with AC97 Pullups on MMC connector Limited speed on SPI bus in block mode (Errata #13). Initial USB Functionality USB host port #2 not connected in TQFP package

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Jtag Reset
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The JTAG TRST reset pin must get a valid reset at startup If not the CPU may or may not boot properly. Freezing spray or heating up CPU may release CPU
- Real issue is lack of JTAG reset

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JTAGSEL Signal
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This signal allows to select the use of the JTAG Port: A low level on the JTAGSEL allows to select the ARM9's ICE A high level on the JTAGSEL allows to select the Boundary Scan function.

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NWAIT
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A low level input on NWAIT (PC6) disables the CPU clock. This does not depend on the PIO A setting. Setting PC6 in PIO Mode will not disable the NWAIT function
- see the AT91RM9200 errata

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Crystal on XIN/XOUT
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If the crystal has a nominal frequency of less than 8 MHz, then a 1 kohm series resistor should be connected to the XOUT pin.

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Reset Pulsewidth
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The CPU needs a power up reset pulse of 900 ms.

- This is to cover the 32 kHz oscillator startup.

Warm reset (when 32 kHz oscillator is running) is 92 us. Most reset circuits generate less Reset Circuits with > 1 s, can generate up to 3 seconds
- The MAX6390 used on the DK is 1120 .. 2420 ms.

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The DS1834AS on the AT91RM9200EK is outside the spec.

- Known bug of the EK. (300 ms only). - Typical oscillators starts up in 350 ms so it normally works anyway.

ATtiny13 as system MCU? Texas Instruments TPS3803?

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ATtiny13 can be used for

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Power On Reset
- Precise Reset width

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Brownout protection Watchdog Reset Button

Debounce Short pulse Medium Pulse Long pulse (< 2 s) normal reset (2..10 s) Turn On/Off Watchdog (> 10 s) Set BMS high - force into Boot Monitor

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LED Status Larger AVRs can be used to increase functionality. Application code available from ulf@atmel.com
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ATtiny13 Block Diagram

+ LED /RESET

BMS + ATtiny13 WDOG_ENA WDOG SWITCH

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Enabling Buffers on the databus

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The Buffer Enable is using SDRAMCS inverted If there is no SDRAM access, then the system accesses the rest of the system SDRAMCS is asserted during SDRAM refresh.
- Conflict if CPU is accessing something else in parallel

Workaround: Qualify with all chip selects

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Adress Bus 24
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Not routed on the chip Maximum contiguos memory is 16 MB A 32 MB memory needs to use [A25,A23..A1]
- Will create a 16MB hole between two 16 MB memory areas

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BMS (Boot Mode Select) pin

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BMS = 0
- The CPU boots from external 16 bit Flash memory - Can be jumpered to 1 during production/upgrade
Allows simple flash programming

BMS = 1
- CPU boots from the internal bootROM - No jumper needed for production programming

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SDRAM controller
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A2 on the CPU shall be connected to A0 on the SDRAM The SDRAM Controller datasheet shows A0 connected to SDRAM A0 The SDRAM controller is however routed through the External Bus Interface which shifts the SDRAM controller A0 to the A2 pin of the chip

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CompactFlash interface
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Only functional in memory mode on the DK. Buffers Enable need to take care of more signals
- See FAQ at http://www.atmel.com/

Interrupts from card not supported on the DK, Neccessary in most case Early AT91RM9200DKs had layout bugs on the CF interface
- /RD, /WR swapped etc.

True-IDE requires extra decoding - not supported by CPU

- See IDE Application Note
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AC-97
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AC-97 requires a clock speed of 24.xx MHz. The SSC cannot run that fast and only supports one timeslot in each direction. Workaround is to use I2S codec with less functionality. AC-97 needs several timeslots. May be difficult to handle. Atmel is designing an AC97 controller for future chips.

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Pullup on MMC connector

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The pullups on the DK are the wrong values for MMC_CMD Trig on the first low to high transition of the CMD signal, use analog input on scope. While the bus is in open-drain mode (and 400kHz clk), the CMD signal looks like a RC low-pass filter with tau somewhere around 0.25 us, which is too slow. The most important issue was to pull-up the MMC_CMD line with a rather small resistor. (my temporary fix is to use a 2k2 pull-up resistor - this is probably NOT a good long term solution) The EK and DK does not use the same signals for this mux EK=PB22, DK=PB7

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Limited Speed of SPI in block mode

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Errata #13 causes the SPI chip select to go inactive if the PDC does not get enough cycles. Only happens on block transfers Never happens on 8/16 bit transfers Dataflashboot 1.02 siffers from the problem, needs update! Typically happens during heavy networking activity
- WLAN on Compactflash

Workaround:
- Reduce the speed of SPI (4 Mbps seems OK) - Force CS low using external H/W

Errata #13 is fixed on new parts

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UART
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When using flow control, speed is limited to 750 kBAUD When Hardware Handshaking is used and if CTS goes low near the end of the start bit of the transmitter, a character can be lost. Problem CTS must not go low during a time slot occuring between 2 Master Clock periods before the starting bit and 16 Master Clock periods after the rising edge of the starting bit. Fix/Workaround
- Use the Falling Edge of SCK to sync the CTS signal - Use the Falling Edge of TXD to clock a flip flop to assert Connect the CTS to the asynch set/clear of the flipflop to deassert

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TWI
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The TWI Linux 2.4 driver has significant problems TWI under 2.6 is significantly better Still random errors occur Recommendation:
- Solder two 10pF capacitors very next to the AT91RM9200
Between SDA and ground Between SCL and ground

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Initial USB functionality in BootROM

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The BootROM assumes that the CPU has an 18.432 MHz XTAL USB will not be functional with another XTAL frequency
- USB DFU is not available when another speed is used.

UART download is OK, due to Autobaud feature.

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USB Host Port #2 not connected

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Only affected in TQFP version Linux 2.4 will report an error on host port #2 Believe fixed in Linux-2.6 S/W workaround

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USB Host Power Management

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Nothing Implemented on the EK.

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AT91RM9200EK schematics Capacitors

5V Vbus monitoring

not needed

1.5K

Pull-up is active by default after reset

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Pull-up is active by default after reset (required by the boot application) No pull-down: DM is floating when the peripheral is disconnected The application shall monitor Vbus to remove the pull-up when the host switches off
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USB Client
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Cannot be bus powered Required to handle pullup on USB bus within 100 ms Reset time is 900 ms. Also hard to handle suspend current of 500 uA.

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Recommended Layout
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Atmel does not supply a recommended layout at this time.

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Recommended solder temp profile

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All our products are compliant with JEDEC J-STD-20 Reflow profile, and the moisture sensitivity to this product is LEVEL 3 with 220C max reflow temperature. This is for CI parts (not RoHS)

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Battery Backup of RTC

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RTC is not backed up. May need external RTC on the AT91RM9200. Is fixed on later generation chips like the AT91SAM9261

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If the 32 KHz does not work!!!

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TST0,TST1 must be connected to Ground

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Ethernet Clock
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Using a clock generated by the onchip PLL is not advisable Use a separate crystal for the Ethernet PHY.
- Check with your PHY vendor

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AT91RM9200 Ethernet Packet Loss

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Some switches cannot handle 100 Mbit Full Duplex properly The problem only occurs when connecting through a low cost Ethernet switch (D-Link DGS-1008 etc.) Multicasting is especially problematic. They had set originally set the PHY to 100 Mbit Full Duplex. The switch starts auto-negotiation, detects the 100 Mbps speed and configures itself as 100 Mbit Half-Duplex.The mismatch betweent the AT91 FD and the switch HD results in packet loss. Strapping the PHY to auto-negotiation or half-duplex seems to resolve the problem.

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Flash
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The AT91RM9200 can work with Parallel or serial flash Serial Flash = Dataflash or Serial EEPROM. Serial EEPROM is not available on the AT91SAM9261. Dataflash has smaller footprint Available up to 64 Mbit today (August 2005). 128 Mbit soon to be released (2006?) 8 pin SO footprint (CASON package) Supported on U-boot/Linux 2.6.12 (JFFS2 support) Atmel has 32/64/128 Mbit parallel flash (also Strataflash 2nd src)
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Investigating SDRAM problems

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Several problems can *appear* to be SDRAM related

- Actually isn't.

Symptom:
- CPU sometimes getting bad data from the SDRAM. - Setting the CPU/MCK ratio to 90/45 makes the problem go away.

Crashing in random places:

- Some voltage or current supply is usually marginal. - Something happens which causes the CPU to draw extra current

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Investigating SDRAM errors

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Check your CPU and PLL voltage supplies for glitches and dropouts around the time of the error.
- We changed/removed an inductor near the PLL circuit and the problem went away.

Run all memory tests from the CPU's internal memory

- Perform full memory tests
(Needs modified Romboot/DataflashBoot to do this).

- Run at full speed, not the default 48 MHz master clock

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Investigating SDRAM problems

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If you based your board on the DK, then you would be initializing the SDRAM in ROMBOOT so you can transfer U-Boot from Dataflash to the SDRAM, and then run U-Boot from SDRAM. U-Boot should not configure the SDRAM. Is this the case? Did you set/change your CPU/master_clock ratio correctly?
usually is 180/60 e.g. 90/45 is a good setting to try. You have to make the change in romboot and in u-boot/include/configs/yourboard.h

Have you tried running at a slower speed?

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Have you double checked you SDRAM clock? usually is 60MHz Did you calculate SDRAMC_CR correctly? Did you calculate SDRAMC_TR correctly? Did you set the bus width correctly? Does it always crash in the same place?
if it does, then you can probably isolate it.

Do other boards crash in exactly the same place?

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Running the AT91RM9200 at full speed

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Program the PLL and enable it. Write to CP15 to switch from Fast Clock to Asynchronous Clock Enable the Instruction Cache Enable the MMU (Without the MMU, the Data cache is disabled) Enable the Datacache Ensure that the MMU page table entries are cacheable. Ensure minimum waitstates are used NWAIT must not be floating

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Enabling cache
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If the PDC writes to an area of memory which is already inside the datacache, the PDC values will not be visible until the cache is flushed! Set the PDC buffers to be non-cacheable in the page tables.

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AT91SAM9261 JTAG Speed

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The AT91SAM9261 starts from 32 kHz The ARM926E core inside uses a synchronous JTAG Interface
- Max JTAG Speed (using J-Link) = CPU clock / 6

32.768 kHz / 6 = 5.45 kHz Only an issue if you do not use SAMBA BootROM and try to load the initial program using JTAG

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ATSAM9261 BMS Pulldown

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The Boot Mode Select pin "Rpullup" has a typo in the datasheet (page 606). It claims: Minimum: 70kOhm, Typical: 10kOhm, Maximum: 175kOhm... Early tests point to 15 kOhm. 1 kOhm pulldown was neccessary for one customer to force booting from external memory

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AT91SAM9261 Watchdog
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The BootROM disables the Watchdog PERMANENTLY If the Watchdog is needed, then the BootROM cannot be used
- A possible workaround is to use an external Watchdog

This is an official Errata

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SAM9261 Battery backup

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The CPU needs to have ~1.2V operation. A clock battery is 1.5V

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SAM9261EK Embedded trace

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While the PCB supports the Embedded Trace, the connector is not mounted on board

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AT91SAM9261EK Dataflashcard support

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If the jumper J21 is in the 1-2 position

- NPCS0 is connected to the internal dataflash

If the Jumper J21 is in the 2-3 position

- NPCS0 is connected to the dataflashcard - It is ALSO connected to NPCS3

When J21 2-3 is connected, the NPCS3 output must be disabled

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AT91SAM9261EK Dataflashcard support

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The AT91SAM9261 BootROM disables NPCS3 Dataflashboot and U-Boot does NOT disabled NPCS3.
- It is currently not useful to connect J21 2-3

Dataflashboot and U-Boot must reside on the internal flash

- Fix is simple though

When J21 is 1-2, the Dataflashcard is available on NPCS3

- Address 0xD000_0000

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AT91SAM9261EK recommended Dataflashcard connection

NPCS0 NPCS0 DF_CS DF_CS

DFC_CS NPCS3 DFC_CS NPCS3

Current Implementation

Proposed Implementation

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