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USE OF MICROPROCESSORS
They are included in almost any electronic device: computers , digital video cameras , vehicles and in many domestic appliances such as washing machines, microwave ovens. With intelligent control technologies, those devices are converted into smart , computerized electronic devices.
GOAL
We aim at developing a basic 32-bit microprocessor which can compute basic mathematical operations such as addition , shifting and storing data.
What is ARM ?
It is a 32 bit reduced instruction set computer instruction set architecture developed by ARM holdings . It was known as advanced RISC machine before. By simplifying the instructions we can provide high performance and much faster execution of each instruction.
Block diagram
REGISTERS
It is a small amount of storage available on CPU whose contents can be accessed quickly. Data is loaded into the registers for temporary storage , manipulated by performing operations on the data and is stored back into the memory. ARM has 16 general purpose registers each of 32-bit.
module regf( input [3:0] readAddr, writeAddr, input [31:0] writeData, input writeEnable, clock, reset,increment, output reg [31:0] readData ); reg [31:0] increment_value [0:0]; reg [31:0] mem [15:0] ; integer i; always @ (posedge clock or posedge reset) begin if (reset == 1'b1) begin for(i=0; i<15; i=i+1) end else if (writeEnable)
CODE
begin if(increment) begin increment_value[0] <= writeData+1; mem[writeAddr] <= increment_value[0]; end else begin mem[writeAddr] <= writeData; end end end always @ (posedge clock) begin if ((readAddr==writeAddr)&&writeEnable) begin readData <= writeData ; end else begin readData <= mem[readAddr] ; end end endmodule
Adder
In a parallel arithmetic unit All 2n input bits available at the same time Carries propagate from the FA in position 0 (with inputs x0 and y0) to position i before that position produces correct sum and carryout bits Carries ripple through all n FAs before we can claim that the sum outputs are correct and may be used in further calculations
Code
module add(sum_out, carry_out, a, b, carry_in); output [31:0] output carry_out; input [31:0] input carry_in; wire [6:0] ripple; sum_out; a, b;
full_adder f_a0(sum_out[3:0], ripple[0], a[3:0], b[3:0], carry_in); full_adder f_a1(sum_out[7:4], ripple[1], a[7:4], b[7:4], ripple[0]); full_adder f_a2(sum_out[11:8], ripple[2], a[11:8], b[11:8], ripple[1]); full_adder f_a3(sum_out[15:12],ripple[3], a[15:12], b[15:12], ripple[2]); full_adder f_a4(sum_out[19:16], ripple[4], a[19:16], b[19:16], ripple[3]); full_adder f_a5(sum_out[23:20], ripple[5], a[23:20], b[23:20], ripple[4]); full_adder f_a6(sum_out[27:24], ripple[6], a[27:24], b[27:24], ripple[5]); full_adder f_a7(sum_out[31:28], carry_out, a[31:28], b[31:28], ripple[6]); endmodule module full_adder( sum, cout, in_a, in_b, cin ); parameter reg_size = 4; input cin; input [reg_size-1:0] in_a; input [reg_size-1:0] in_b; output [reg_size-1:0] sum; output cout; assign {cout,sum} = in_a + in_b + cin; endmodule
Barrel Shifter
It is a digital circuit that can shift a data word by a specified number of bits in one clock cycle. It can be implemented as a sequence of multiplexers.
Block Diagram
Operand 1 Operand 2
Barrel Shifter
ALU
Result
code
module barrel_shift( input C,SI,left_right, input [31:0] no_of_shift, output [31:0] SO ); reg [31:0] tmp; initial begin tmp=32'b0; end always @(posedge C) begin if(left_right == 1'b1) begin tmp = tmp << no_of_shift; tmp[0] = SI; end else begin tmp = tmp >> no_of_shift; tmp[31] = SI; end end assign SO=tmp ; endmodule
Multiplexer
A multiplexer or mux is a device that selects one of the several analog or digital input signals and forwards the selected input into a single line. A mux of 2n inputs has n select lines which are used to select which input line to send to the output.
Block Diagram
Goals Achieved
We have implemented the Datapath ALU(Arithmetic and logical operations both) Adder Subtractor Barrel Shifter OR,XOR,AND Registers Multiplexers
Control Unit
Instruction Register Decoder Program Counter
CONTROL UNIT
WORKING
1.Instruction is divided into three cycles: T0:Fetch T1:Decode T2:Execute Instruction is fetched from memory(ROM) where it is stored . After fetching the instruction program counter is incremented by one and instruction is decoded followed by execution.
OUTPUT
We fed a sample program for generating Fibonacci series in our processor and got the result as shown in the next slide .
RESULT
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