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Microprocessors 1-1
Interrupts Programming
An interrupt is an external or internal event that interrupts the microcontroller to inform it that a device needs its service. Interrupts vs. Polling A single microcontroller can serve several devices. There are two ways to do that:
interrupts polling.
The program which is associated with the interrupt is called the interrupt service routine (ISR) or interrupt handler.
M_Nokhodchian @ yahoo.com Microprocessors 1-2
Upon executing the RETI the microcontroller returns to the place where it was interrupted. Get pop PC from stack
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Microprocessors 1-3
Interrupt Sources
Original 8051 has 6 sources of interrupts
Reset Timer 0 overflow Timer 1 overflow External Interrupt 0 External Interrupt 1 Serial Port events (buffer full, buffer empty, etc)
More timers, programmable counter array, ADC, more external interrupts, another serial port (UART)
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Microprocessors 1-4
Interrupt Vectors
Each interrupt has a specific place in code memory where program execution (interrupt service routine) begins.
External Interrupt 0: Timer 0 overflow: External Interrupt 1: Timer 1 overflow: Serial : Timer 2 overflow(8052+) 0003h 000Bh 0013h 001Bh 0023h 002bh
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Microprocessors 1-5
main 03H int0sr 0BH t0sr 13H int1sr 1BH t1sr 23H serialsr 30H
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Microprocessors 1-7
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Microprocessors 1-8
Example
A 10khz square wave with 50% duty cycle
ORG LJMP ORG T0ISR:CPL RETI 0 MAIN 000BH P1.0
;Reset entry poit ;Jump above interrupt ;Timer 0 interrupt vector ;Toggle port bit ;Return from ISR to Main program ;Main Program entry point ;Timer 0, mode 2 ;50 us delay ;Start timer ;Enable timer 0 interrupt ;Do nothing just wait
Microprocessors 1-9
ORG 0030H MAIN: MOV TMOD,#02H MOV TH0,#-50 SETB TR0 MOV IE,#82H SJMP $ END
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Example
Write a program using interrupts to simultaneously create 7 kHz and 500 Hz square waves on P1.7 and P1.6.
8051 P1.7
143s 71s
2ms
P1.6
1ms
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Microprocessors 1-10
ORG LJMP ORG LJMP ORG LJMP ORG MAIN: MOV MOV SETB SETB MOV MOV SJMP T0ISR: CPL RETI T1ISR: CLR MOV MOV SETB CPL RETI END
0 MAIN 000BH T0ISR 001BH T1ISR 0030H TMOD,#12H TH0,#-71 TR0 TF1 IE,#8AH IE,#8AH $ P1.7
Solution
8051 P1.7
143s 71s
2ms
P1.6
1ms
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Microprocessors 1-11
Timer ISR
Notice that
There is no need for a CLR TFx instruction in timer ISR 8051 clears the TF internally upon jumping to ISR
Notice that
We must reload timer in mode 1 There is no need on mode 2 (timer auto reload)
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Microprocessors 1-12
IE1
(LSB) IT0
Microprocessors 1-13
External Interrupts
Level-triggered (default) INT0 (Pin 3.2) 0 1 2 IT0 IE0 (TCON.3) 0003
Edge-triggered
Edge-triggered
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Microprocessors 1-14
WAIT:
ORG 0013H SETB P1.1 MOV R0,200 DJNZ R0,WAIT CLR P1.1 RETI
ORG 30H MAIN: SETB IT1 ;on negative edge of INT1 MOV IE,#10000100B WAIT2: SJMP WAIT2 END
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Microprocessors 1-16
Skip: end
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Interrupt Priorities
What if two interrupt sources interrupt at the same time?
IP.7: reserved IP.6: reserved IP.5: timer 2 interrupt priority bit(8052 only) IP.4: serial port interrupt priority bit IP.3: timer 1 interrupt priority bit IP.2: external interrupt 1 priority bit IP.1: timer 0 interrupt priority bit IP.0: external interrupt 0 priority bit
M_Nokhodchian @ yahoo.com Microprocessors 1-19
MOV IP , #00000100B
1. 2. 3. 4. 5. Int1 Int0 Timer0 Timer1 Serial Int1 Timer1 Int0 Timer0 Serial
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Microprocessors 1-20
A high-priority interrupt can interrupt a low-priority interrupy All interrupt are latched internally Low-priority interrupt wait until 8051 has finished servicing the high-priority interrupt
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Microprocessors 1-21