Virtual Memory

Invented on Manchester atlas 1962

It embodied many pioneering features, which we now take for granted. These include system features such as, Timesharing of several concurrent computing and peripheral operations, Multiprogramming, and the One-Level Store (Virtual Store). Design features included, High-speed arithmetic, Asynchronous control, interleaved stores, paging, Fixed store (ROM), and autonomous transfer units. These both required and enabled Software developments such as the Supervisor (Operating System), the Compiler-Compiler and High level languages.

Reason was economic

Two technologies were available Magnetic cores and Magnetic drums The economics of the available store technology was quite simple. One bit of Magnetic Core store cost three shillings whilst one bit of magnetic drum store cost six pennies. Core was six times more expensive than drum. Therefore the main storage was a combination of the two technologies.

Core store

It consisted of several stacks. Each stack had 4096 words of 48 bits operating with a cycle time of 2 microseconds. Arranging the store into pairs of stacks, with a selection mechanism for each stack reduces the effective access time. Each pair consists of an Even and an Odd stack. The even stack contains words with even addresses and the odd stack the words with odd addresses. Consecutive words in a block are thus stored alternately in even and odd stacks of the pair containing the block.

1971 Ladybird book of computers for primary schools

Pages
Each block consisted of 512 words and was contained in a page of the core store. There were 16 pages in each pair of stacks.

Drum store
The Magnetic Drum Store was the backing store. There were four drums each of 24k words, giving a total of 96k words. The revolution time was 12 milliseconds, a drum latency of six milliseconds. The rate of transfer was one block of 512 words per two milliseconds.

Lady bird book drum store

One Level Store

The Drum and Main Core Store were referred to as the Main Store of the machine. Words within this store were addressed in blocks of 512 words up to 192 blocks, the drum capacity. When a block was transferred into a page of the core store, the block address was recorded in a Page Address Register located in the core store controller.

Page address registers

There were 32 such registers, one for each page in the core store. When an address was decoded as referring to a word in the store, the block address bits were compared with the Page Address Registers.
high low

Associative memory access

PAR PAR PAR PAR PAR

page

Page faulting
If the block was in the core store an Equivalence signal would cause the word transfer to occur. If the block was not down in the core store a Non Equivalence signal would cause the main program to be held up, or interrupted, and a drum transfer routine entered to bring the block down from the drum. After the drum transfer the main program would continue and this time an Equivalence signal would permit the word transfer.

Fault handler
The page fault handler was held in a separate read only memory or ROM 1. It reads in a page from drum into a core page 2. It loads the page address register with the pages drum address 3. It returns from interrupt

Retry
At this point the instruction restarts and in this case one PAR returns Equivalence Enables the read Note that the PAGE FAULT interrupt must return to the instruction that caused the fault. This is unlike an ordinary interrupt that returns to the next instruction

Intel 286 first micro with virtual memory

286 registers
General Purpose Registers Segment Registers

AH/AL BH/BL CH/CL DH/DL

AX BX CX DX

Accumulator Base Counter Data

CS Code Segment DS Data Segment SS Stack Segment ES Extra Segment

Stack Registers SP Stack Pointer BP Base Pointer

Pointer Registers SI Source Index DI Destination Index IP Instruction Pointer

Segmented addressing
All addresses were 32 bits long and split into two parts Segment:Offset Each was 16 bits in length The Segment came from a segment register and the Offset from a pointer register, or a constant in the instruction

Examples
Mov ax, DS:100h
loads word at 100hex in the data segment into ax Add ax,ES:[SI] adds the word in the Extra segment at the offset in the SI register to the ax register

Virtual memory
A 286 expanded addressable physical memory to 16MB and addressable virtual memory to 1GB. This was done by using the segment registers only for storing an index to a segment table. There were two such tables, the GDT and the LDT, holding each up to 8192 segment descriptors, each segment giving access to up to 64 KB of memory.

Segmented vm

Look up descriptor table

On the 386, 486 and 586 offset is 32 bits, on 286 it was 16

Segment selector
A selector is loaded into the segment register and triggers the acces to the segment tables

Fault on load seg reg

The virtual memory fault occurs when the segment register is loaded. Thus Mov es,ax moves ax to the es register.
If the segment table shows the segment as being absent there will be an interrupt

Hidden and visible parts

Segment registers have a hidden part that is loaded by hardware when the user loads the selector field

Segment descriptors
The segment tables contain descriptors to the segments

Protection
Attempt to access beyond segment limit causes segment fault Unlimited recursion on routine cause stack segment fault Attempt to execute data segment cause fault Attempt to write to code segment will cause fault

2 level translation ( from 386 on)

seg offset 48 bit

Segmentation mechanism

Linear addr

32 bit

Paging mechanism

RAM addr < 32 bit

Page table mechanism

Page directory entry

Contrast
Segments
Variable sized Strongly typed

Pages
Fixed size Weakly typed

Why two mechanisms

Two different operating system design philosophies IBM OS/2 and early versions of Windows used segments Linux and recent versions of Windows use only the paging system
This was a hangover from the DEC Vax processor from which they were ported which had only pages

Efficiency
Key feature of any VM system is that one must make memory access fast. You can not afford multiple real memory acceses for each virtual memory access attempted by the program Atlas got round this by using associative memory registers

Segment approach
The segmented memory system gains efficiency by only doing a check when the segment register is loaded. It can then be used many times : For example, point the segment register at the base of an array, then subsequently each individual array access has no overhead.

Page translation cache on Pentium

Linear addr registers

On chip associative page address registers. This is small, only about 64 of them
Physical address Chip boundary

Use of the page trans cache

This is similar to the approach of the Atlas except that the associative registers are loaded by hardware from the page directory in main memory. A software interrupt only occurs if the page directory marks page as absent Most memory accesses are within a page and so use only the associative registers