M.

Kavya Roll no 09

 About

integrated circuits Moores law Introduction to vlsi Brief introduction to vhdl conclusion

Integrated Circuits (IC) Meaning That All The Components In This Circuits Are Fabricated On The Same Chip. ICs Have Become A Vital Part Of Modern Electronics Circuits Design. They Are Used In The Computer Industry, Automobile Industry, Home Appliances, Communication And Control Systems. ICs Are Of Two Basic Types :

1. 2.

Digital ICs Linear ICs

 Digital

ICs Are Complete Functioning Logic Network That Equivalents Of Basic Transistor Logic Circuits. They Are Used To Form Such Circuits As Gate,coutner,mux, Demux, Register,etc. Digital Circuits Concerned With Only Two Levels Of Voltage High And Low. Digital Ckts Are Easy To Design And Produce In Large Quantities As Low Cost Devices.

 Linear

ICs Are Equivalent Of Discrete Transistor Networks Such As Amplifier,Filter,Frequency Multipliers And Modulators. It Requires Extra Components for Satisfactory Operations. In Linear Ckts The Output Of Electrical Signals Vary In Proportion To The Input Signals Applied. Linear Ckts Are Also Referred To As Analog Circuits.

 Moore

Who Is Known As Father Of Printer. In 1970 Moore Gave The Law Which Is Known As Moores Law. Its State That After Each 18\24 Months The Number Of Components Is Doubled In IC's . For Example Intel Processor P4 After Two Years Later Comes Core 2 Dual ,But Processor Dual Core Comes In Just Sixth Months Later So The Average Is 18 Months.

PROCESSORYEAR OF NUMBER OF INTRODUCTI TRANSISTORS ON 4004 1971 2300 8008 1972 3500 8080 1974 6000 8085 1976 6500 8086 1978 29000 8088 1979 29000 80286 1982 134000 80386 1985 275000 80486 1989 1.2M PENTIUM 1993 3.1M PENTIUM II 1997 8.8M PENTIUM III 1999 9.5M PENTIUM 4 2000 42M

INITIAL CLOCK SPEED 108KHz 200KHz 2MHz 5MHz 5MHz 5MHz 8MHz 16MHz 25MHz 150MHz 233MHz 650MHz 1.4GHz

TECHNOLOGY
INVENTON OF TRANSISTOR
DISCREATE COMPONENTS

NO. OF TRANSISTER PER CHIP

YEAR

1
1

1947
1950

SMALL SCALE INTEGRATION

MEDIUM SCALE INTEGRATION LARGE SCALE INTEGRATION

10
100-1000 1000-20,000

1961
1966 1971

VERY LARGE SCALE INTEGRATION

ULTRA LARGE SCALE INTEGRATION

20,000-1,00,000
1,00,000-10,00,000

1980
1990

GIANT SCALE INTEGRATION

>10,00,000

2000

VLSI Is A Process Of Integration Of Millions Of Transistor In A Single Chip .Vlsi Design Involves All Aspects Of Creating An IC's. Vlsi Design Process Is Classified Into Two Categories . Front End And Back End . In Front End Vlsi Design Process A Design Engineer Performs All Aspects Of Design Before Handling The Design. In Back End Vlsi Design Process Tasks Performed By Design Engineers Are (A) MASK GENERATION (D)testing (B)wafer PROCESSING (E)delivery OF SAMPLES (C)packaging (F)final MASS PRODUCTION

 Vhdl

Is One Of The Most Accepted And Widely Used Language For Describing Digital System. Vhdl Has Been Approved By Ieee As A Standard Language For Designing Hardware. Vhdl Is A Large And Verbose Language With Many Complex Constructs And It Is Initially Difficult To Understand. However It Is Possible To Quickly Understand A Sub Set Of Vhdl Which Is Both Simple And Easy To Use. Vhdl Is Abbreviation For Vhsic Hardware Description Language.

 Sequential

Language Concurrent Language Net- List Language Timing Specifications Waveform Generation Language

 (A)

Labour (B) Cost (C) Material (D) TIME

DESIGN IDEA VHDL MODLE SIMULATION SIMULATED WAVEFORMS

SYNTHESIZER CIRCUIT GENERATED CIRCUITED IMPLEMENTED

LIBRARY/PACKAGE ENTITY ARCHITECTURE

 (A)

ENTITY DECLARATION (B) ARCHITECTURE BODY (C) CONFIGURATION DECLARATION (D) PACKAGE DECLARATION (E) PACKAGE BODY

ENTITY: AN ENTITY IS THE MOST BASIC BUILDING BLOCK IN A DESIGN. A HARDWARE DESCRIPTION OF A DIGITAL SYSTEM IS CALLED AN ENTITY. AN ENTITY SPECIFIES THE EXTERNAL VIEW AND ONE OR MORE INTERNAL VIEWS.
ARCHITECTURE BODY: THE ARCHITECTURE BODY CONTAINS THE INTERNAL DESCRIPTION OF THE ENTITY. THE ARCHTECTURE DESCRIBES THE FUNCTIONALITY & BEHAVIOUR OF THE ENTITY. AN ARCHITECTURE IS ALWAYS RELATED TO AN ENTITY.

CONFIGURATION: IT SPECIFIES THE BINDING OF ONE ARCHITECTURE BODY FROM THE MANY ARCHITECTURE BODIES. CONFIGURATION DECLARATION IS USED TO BIND ONE OF MANY ARCHITECTURE BODIES TO AN ENTITY. IT IS ALSO USED TO BIND COMPONENTS USED IN STRUCTURAL MODEL TO OTHER ENTITY ARCHITECTURE PAIR. AN ENTITY MAY HAVE ANY NUMBER OF DIFFERENT CONFIGURATION. PACKAGE: A PACKAGE IS A COLLECTION OF COMMONLY USED DATA TYPES AND SUB PROGRAMS USED IN A DESIGN.

PACKAGE DECLARATION: A PACKAGE DECLARATION ENCAPSULATES A SET OF RELATED DECLARATIONS SUCH AS DATA TYPES, COMPONENTS, SUB PROGRAM (PROCEDURE AND FUNCTIONS). THE DECLARATION INSIDE A PACKAGE CAN BE SHARED BY OTHER DESIGN UNITS BY USING A USE CLAUSE. PACKAGE BODY: A PACKAGE BODY CONTAIN THE DEFINITIONS OF SUBPROGRAMS DECLARED IN A PACKAGE DECLARATION. NAME OF PACKAGE BODY SHOULD BE SAME AS PACKAGE DECLARATION

ENTITY DECLARATION :
Entity Declaration Describes How An Entity Is Connected To Outside World. It Describes The External View Of The Entity. Entity Declaration Specifies The Name Of Entity. It Also Specifies The Input And Output Ports Through Which Entity Communicates With The External World. SYNTEX OF ENTITY DECLARATION : ENTITY entity-name IS PORT (port1: port1-type: port2: port2-type);

END entity-name;

Entity Declaration For a 2 Input And Gate. entity AND2 is port (a, b: in bit ; c : out bit); end AND2;

ENTITY DECLARATION FOR A FULL ADDER. entity Full Adder is port (X, Y, Cin: in bit; -- Inputs Cout, Sum: out bit); -- Outputs end Full Adder;

Full Adder

ARCHITECTURE :
It Shows The Inside View Or What Are The Functions Operation Are Done And Which Type Of That . An Architecture Is Always Related To An Entity & Describes The Behaviour Of The Entity.

Internal Details Of An Entity Are Specified By An Architecture Body By Using Any One Of The Following Model:
SYNTEX OF ARCHITECTURE: ARCHITECTURE arcitecture-name OF entityname IS

.declare some signals here

BEGIN .put some concurrent statement here END architecture-name;

The Behavioral Style Of Modeling Specifies The Behavioral Of An Entity As A Statements That Are Executed Sequentially In The Specified Order. All Statements Which Are Specified Inside A Process Statement, Do Not Clearly Specifies The Structure Of The Entity But Merely Its Functionality. A Process Statement Is A Concurrent Statement That Can Appear With In An Architecture Body.

THE BEHAVIORAL MODEL DESCRIPTION OF AND GATE . architecture AND-2-BEHAVIOR of AND-2 is begin process (A,B) begin C<=A and B; end process; end AND-2 BEHAVIOR;

In The Structure Style Of Modeling An Entity Is Described In Terms Of Its Components And Their Interconnections. A Structure Model Does Not Tell About The Functionality Of The Entity. A Structure Description Is Easiest To Be Synthesized. The Architecture Body Is Composed Of Two Parts: The Declaration Part (Before The Keyword Begin) The Statement Part (After The Keyword Begin). Half Adder Is Such Type Of Structure Architecture.

architecture HALF-ADDER-STRUCTURE of HALF-ADDER is component AND2 port(IN1,IN2: in bit ; OUT1: out bit); end component;
component XOR2 port(IN3,IN4: in bit ; OUT2 : out bit); end component; begin A1:AND2 port map (A,B, Sum); X1:XOR2 port map (A,B,Carry); end HALF-ADDER-STRUTURE;

In The Dataflow Style Of Modeling An Entity Is Described In Terms Of Data Flow By Using Concurrent Signal Assignment Statements. A Dataflow Model Does Not Tell About The Structure Of The Entity. DATAFLOW DESCRIPTION OF HALF ADDER. architecture HALF-ADDER-DATATFLOW of HALF-ADDER is begin SUM<=A xor B; CARRY<=A and B; end HALF-ADDER-DATAFLOW;

 entity

AND2 is port (a, b: in bit ; c : out bit); end AND2;

architecture begin c

beh of AND2 is

<= a and b; end beh;

OUTPUT WAVE FORM

OUTPUT WAVE FORM

OUTPUT WAVE FORM

THANK YOU