Rambus Seminar

Equalization & Clock Recovery for a 2.
5-10 Gb/s 2PAM/4PAM Backplane Transceiver Cell
May 2, 2003 Fred Chen Sr. Member of Technical Staff Rambus Inc.
Agenda
The Backplane Environment PAM2 vs. PAM4 signaling Link Design Simulation & Measured Results Conclusions
UC Berkeley BWRC Seminar
The Backplane Environment

Package
Line card trace
On-chip parasitic (termination resistance and device loading capacitance) Back plane connector Line card via
Back plane trace
Backplane via
There are many sources of Z and thus many possible sources of reflections
Board Material Loss Counter Bored Backplane Vias
Backplane Component Effects
PCB only
PCB + Connectors
Device parasitics alone can cause addl 5dB loss at high frequencies
PCB, Connectors, Via stubs & Devices
Variations Within a Backplane
Four channels from a single FR4 backplane There are large variations between channels
Single Bit Response

E u liz d&Ue u liz dS g B Rs o s qa e n q a e in le it e p n e
08 .0
0 .9 0 .8 0 .7 0 .6 0 .5 V
V
06 .0 04 .0 02 .0 0 - .0 02 - .0 04
Iimpact of reflections
increases when relative to equalized eye Wworst-case sequence can sum all reflections
0 .4 0 .3 0 .2 0 .1 0 - .1 0 0 1 2
- .0 06 - .0 08 0 1 2 3 n s 4 5 6 x1 0
-9
3 n s
6 x1 0
-9
Reflection Sources
TX DATA AT AR B CT CR D
gh-gh conn. (baseline) : Normalized Raw and eq pulse response: PR length after main 60
RX DATA
10
T, T,R R
C A2
T, T,R R
T, T,R R
% of the received main
-2
-4
-6
Primary reflection sources are at the connector/backplane transition

-10 500 1000 1500 2000
-8
Grouped in time as a function of backplane length
Eye With Worst Case Reflections

0 .2 05 .1 0 .1 V oltage [V ] 05 .0 0 - .0 05 - .1 0 - .1 05 - .2 0 -5 1 0 .2 05 .1 0 .1 05 .0 0 - .0 05 - .1 0 - .1 05 - .2 0
-0 1 5 lo p f g d
1 0
0 .5 sc e
1 .5 x1 0
-1 0
(left) 2-PAM probability distribution function (PDF) showing the probability of an eye waveform for each voltage at the sample point (right) equalized eye with worst-case pattern. 6.4Gb/s over 20 backplane.
Agenda
What is 4-PAM
Binary (NRZ) is 2-PAM 2-PAM uses 2-levels to send one bit per symbol Signaling rate = 2 x Nyquist 4-PAM uses 4-levels to send 2 bits per symbol Each level has 2 bit value Signaling rate = 4 x Nyquist
00 0 0 01
11
10
UC Berkeley BWRC Seminar Note
: both can be either single-ended or differential
When Does 4-PAM Make Sense?

Nyquist Frequency (GHz)
0.0 1.0 2.0 3.0 4.0 5.0
-20db
-40db
-60db
First order : slope of S21

3 eyes : 1 eye = 10db loss > 10db/octave : 4-PAM should be considered
|H(f)|
Agenda
The Backplane Environment PAM2 vs. PAM4 signaling Link Design
Equalization Clocking
Simulation & Measured Results Conclusions
Equalization For Loss : Flatten Response
=
Channel is band-limited Equalization : boost high-frequencies relative to lower frequencies
Transmit Linear Equalizer : SBR

0.7 Unequalized Equalization Pulse End of Line
0.5
Voltage
0.3
0.1
-0.1
-0.3 0.0
0.3
0.6
0.9
1.2
time (nsec)
Transmit and Receive Equalization

TX DATA RX DATA
TAP SEL LOGIC
Transmit and receive equalizers are combined to make a range restricted DFE
Tx equalizer functions as the feed-forward filter Rx equalizer restricted in performance of loop
Tx & Rx Equalization Ranges
RX Equalizer 5-17 taps after main Pick any 5 taps
TX Driver/Equalizer : 5 taps 1(pre)+1(main)+3(post)
2-PAM/4-PAM Transmitter
[MSB,LSB] TP TN TN 00 01 11 10
A[2]
TP 4-PAM
4-PAM Encoder
A[1]
00 TN
10
A[0]
TP 2-PAM: LSB=0
Transmit either 2-PAM or 4-PAM using Gray code
5-Tap 2P/4P Transmitter (Original)

TP TN TP TN W/L A[2] W/L A[0] 1/z A[1] W/L B[0] 1/z A[0]
W B[6:0] WA[6:0]
W/L
...
W/L
1/z E[0]
W/L
WE[6:0]
Simple 2P/4P transmitter: Total gate = 3W/L 5-Tap 2P/4P transmitter: Total gate = 15W/L
5-Tap 2P/4P Shared Transmitter

TP TN W/L A[0] 1/z B[0] 1/z
WB[6:0] WA[6:4] WE [6:4]
Shared Driver Segments (7)
A[0] E[0]
Allocation TP TN Logic W/8L
...
...
...
W/L
A[0] E[0]
W/8L
...
W/8L A[0]
W/L
W A[3:0]
E[0]
WE[6:0]
E[0]
WE[3:0]
Total gate = 3(5) = 15W/L

Total gate = 3(7/8+5/8) = 4.5W/L
...
W/8L
1/z
Dedicated Tap Drivers (5)
...
Receive Equalizer
Normal Rx Path Rx Data Sampler Phase Mixer Tap Select Training Sequence 0101... CDR UP/DOWN
Tap Weights
...
Receive Equalizer
...
Calibrate Variable Delay
...
Dual Loop PLL/DLL Design

4,5 Low Pass Filter PD
VCO
TX Clk
Ref Clk
RX Data
CDR Logic
RX Clk
Phase Mixers
Self-biased 4x or 5x RefClk Multiplier based on [Maneatis, Sidiropoulos, Horowitz] CDR is DLL w/PLL vectors & phase mixers 2X oversampling per bit (edge + data) Dual loop design avoids harmonic locking
Multi PAM clock recovery

Data can transition from and to any level 2PAM CDR may lock to any of three strong timing distributions
4-PAM Edges & CDR

Minor Major
00 01 11
LSB thresholds
MSB threshold
10
Timing errors possible if using a 2-PAM CDR on unrestricted 4-PAM data

2-PAM/4-PAM CDR
2PAM/4PAM Mode CDR clk
MSB TranDet
Early/Late
CDR transition selection

LSB TranDet
Tran
Majority Voter
Phase Mixer
Tran(2PAM) = MSBTran Tran(4PAM) = (LSBTran * MSBTran) + (MSBTran * LSBTran)
2-PAM mode - uses major transitions 4-PAM mode - uses minor transitions UC Berkeley BWRC Seminar
Complete Link Block Diagram

SysClk TX Data Parallel to Serial TX EQ Tclk 1/4 or 1/5 RefClk 1 or 1/2 PLL Phase Mixer Phase Mixer Phase Mixer Phase Mixer Rclk Vtt RXP RXN Rclk RX Equalizer Vtt TXP TXN
TX
Clocking
Phase Control RX Data RX Clk Serial to Parallel
RX
Tap Selection
Tap Weights
Agenda
Measured PLL (+TX) Jitter

3.0
2.5
RMS Jitter [%UI]
2.0
1.5
1.0
0.5
2.3psec rms; 18psec p-p @ 3.2GHz

(6.4Gbps @ 2P, 12.8Gbps @ 4P)
0.0 0 1 2 3 4
PLL frequency [GHz]

s Includes on-chip noise
Measured 4-PAM CDR Performance

Phase
2-PAM CDR on 4-PAM data

60ps p-p @ 8Gb/s
Phase
4-PAM CDR uses only minor transitions Lower dither jitter

35ps p-p @ 8Gb/s
Cycle UC Berkeley BWRC Seminar
System Level Simulink Model
TX Equalization Effectiveness
No EQ Un-folded: 10*T w/TX EQ
Folded
20 of FR4 & two connectors
2-PAM eye with no equalization at 6.4Gb/s over 20 BP
2-PAM eye with Tx equalization at 6.4Gb/s over 20 BP
10G Eyes & System Margin Shmoos
3/20/3 = 26 Trace + 2 Connectors Tested to BER < 10-15

Data Level Distribution With No Receive Equalization

0 .2 05 .1 0 .1 Voltage [V ] 05 .0 0 - .0 05 - .1 0 - .1 05 - .2 0 -5 1 0 .2 05 .1 0 .1 05 .0 0 - .0 05 - .1 0 - .1 05 - .2 0
-0 1 5 lo 1 p f g0 d
1 sc e
2 x1 0
-1 0
(left) 4-PAM PDF showing broad distributions and (right) eye including worst-case transitions at 10Gb/s over a 20 backplane.
Data Level Distribution With Receive Equalization

0 .2 05 .1 0 .1 Voltage [V] 05 .0 0 - .0 05 - .1 0 - .1 05 - .2 0 -5 1 0 .2 05 .1 0 .1 05 .0 0 - .0 05 - .1 0 - .1 05 - .2 0
-0 1 5 lo p f g d
1 0
1 sc e
2 x1 0
-1 0
(left) 4-PAM PDF showing narrowed distributions and (right) eye including worst-case transitions showing improvement of both distributions and eyes. 10Gb/s over 20 BP
RX Equalization Effectiveness
No RX Eq With RX Eq
Measured system margin with device shmoo shows large improvement with RX Eq
20 of FR4 & two connectors
Agenda
The Backplane Environment PAM2 (NRZ) vs. PAM4 signaling Link Design Simulation & Measured Results Conclusions
Prototype System Evaluation
Constructed line cards with commercially available and next generation connectors A complete matrix of backplanes was constructed
5 connectors X 3 materials Counterbored/Non-Counterbored vias
System components (packages, vias, connectors, traces, etc.) were individually measured to construct complete channel models
2P/4P Performance by Configuration

2-PAM (NRZ) Maximum Performance (Gbps)
12 10 8 6 4 2 0 Top 20" 12 10 8 6 4 2 0 Top 20" FR4NoCB 0 Bottom 20" FR4NoCB 1 Top 10" FR4NoCB 2 Bottom 10" FR4NoCB 3 Top 20" Nelco6kCB 4 Bottom 20" Nelco6kCB 5 Top 10" Nelco6kCB 6 Bottom 10" Nelco6kCB 7 FR4NoCB 0 Bottom 20" FR4NoCB 1
Configuration Space
s 5 Different connectors
4-PAM Maximum Performance (Gbps)
10" 10" 20" FR4NoCB 2 FR4NoCB 3 Nelco6kCB 4 Top Bottom Top Bottom 20" Top 10" Nelco6kCB 6 Bottom 10" Nelco6kCB 7 Nelco6kCB 5
s 2 Different dielectrics s 2 Different via types s 2 Different Trace lengths s Top & Bottom Layers
Summary & Conclusions

TX PLL
Process Power
RX
0.13 CMOS 40mW / Gb 1mm2 2 6.4 Gb/s 4 10 Gb/s
Area 2-PAM Range 4-PAM Range
Backplane Environment is very challenging

Frequency dependent dielectric and skin loss Many variations between channels Reflection locations in time vary with length and Nyquist Does not scale due to increasing need for complexity
With the right silicon approaches copper backplanes can run at 10Gb/s

Rambus Seminar

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Equalization & Clock Recovery for a 2.

5-10 Gb/s 2PAM/4PAM Backplane Transceiver Cell

UC Berkeley BWRC Seminar

The Backplane Environment

Line card trace

Back plane trace

Backplane Component Effects

PCB, Connectors, Via stubs & Devices

UC Berkeley BWRC Seminar

Variations Within a Backplane

UC Berkeley BWRC Seminar

Single Bit Response

UC Berkeley BWRC Seminar

% of the received main

Primary reflection sources are at the connector/backplane transition

UC Berkeley BWRC Seminar

Grouped in time as a function of backplane length

Eye With Worst Case Reflections

UC Berkeley BWRC Seminar

UC Berkeley BWRC Seminar

UC Berkeley BWRC Seminar Note

: both can be either single-ended or differential

When Does 4-PAM Make Sense?

First order : slope of S21

Simulation & Measured Results Conclusions

UC Berkeley BWRC Seminar

Equalization For Loss : Flatten Response

Transmit Linear Equalizer : SBR

Transmit and Receive Equalization

TAP SEL LOGIC

Tx & Rx Equalization Ranges

RX Equalizer 5-17 taps after main Pick any 5 taps

UC Berkeley BWRC Seminar

TX Driver/Equalizer : 5 taps 1(pre)+1(main)+3(post)

UC Berkeley BWRC Seminar

Transmit either 2-PAM or 4-PAM using Gray code

5-Tap 2P/4P Transmitter (Original)

5-Tap 2P/4P Shared Transmitter

Shared Driver Segments (7)

Allocation TP TN Logic W/8L

Total gate = 3(5) = 15W/L

Total gate = 3(7/8+5/8) = 4.5W/L

Dedicated Tap Drivers (5)

UC Berkeley BWRC Seminar

Dual Loop PLL/DLL Design

Multi PAM clock recovery

UC Berkeley BWRC Seminar

4-PAM Edges & CDR

Timing errors possible if using a 2-PAM CDR on unrestricted 4-PAM data

CDR transition selection

Tran(2PAM) = MSBTran Tran(4PAM) = (LSBTran * MSBTran) + (MSBTran * LSBTran)

Complete Link Block Diagram

Phase Control RX Data RX Clk Serial to Parallel

UC Berkeley BWRC Seminar

Measured PLL (+TX) Jitter

RMS Jitter [%UI]

2.3psec rms; 18psec p-p @ 3.2GHz

PLL frequency [GHz]

Measured 4-PAM CDR Performance

2-PAM CDR on 4-PAM data

4-PAM CDR uses only minor transitions Lower dither jitter

Cycle UC Berkeley BWRC Seminar

System Level Simulink Model

UC Berkeley BWRC Seminar