Design for Testability

Testability Measurement DFT Basics DFT Techniques ad hoc Scan design Boundary scan

What is Testability ?
Def.- Testability is the property of a circuit which allows a test engineer to more easily derive a procedure to accurately determine the functionality of a circuit to a desired degree. Also its a design characteristics that influences various costs associated with testing. Usually it allows for

1) The Status (Normal, Inoperable and Degraded) of a device to be determined and the isolation of faults within the device to be performed quickly, to reduce both test time and cost. 2) The cost effective development of the tests to determine the status.
Can also be defined as the Controllability and Observability of a circuit to determine defects.

Testability
Controllability: The ability to set some circuit nodes to a certain states or logic values. Observability: The ability to observe the state or logic values of internal nodes. Usage of Testability Measures
Speed up test generation Improve the design testability Guide the DFT insertion

Testability Measurement
TMEAS [Stephenson & Grason, 1976]

SCOAP [Goldstein, 1979]

TESTSCREEN [Kovijanic 1979] CAMELOT [Bennetts et al., 1980] VICTOR [Ratiu et al., 1982]

 Sandia Controllability Observability Analysis Program. Using integers to reflect the difficulty of controlling and observing the internal nodes. Higher numbers indicate more difficult to control or observe. Applicable to both combinational & sequential circuits.

These programs compute set of values for each line in a circuit. These values are intended to represent the relative degree of difficulty for computing an input vector or sequence for each of the following problems.

1. Setting line x to a 1 (1-Controlability).

2. Setting line x ro a 2 (0-Controlability). 3. Driving an error from x to a primary output (Observability). Problem1. Large values Implies worse Testability than smaller ones. Sol. To reduce large value, the circuit must be modified; simplest modification deal with adding test and control circuitry. The controllability and observablity of various nodes in a circuit are combined to produce one or more testability values for the circuit.

Problem2. First, The correlation between testability values and test generation costs has not been well established. Second, its not clear how to modify circuit to reduce the value of these testability measures. Sol. Add test points to lines having highest observability values and control circuitry to lines having highest controllability values, are usually not effective. A method for automatically modifying a design to reduce several functions of these testability values, such as maximum values and the sum of values. But the problem with this is to complex.

 Test points Initialization Monostable multivibrators (one shot) Oscillators and clocks Counter / Shift registers Partitioning large circuits Logic redundancy Break global feedback paths

Test Points Rule : to enhance controllability and observability by inserting control points (cp) and observation points (op), respectively.

can be done only for board

 Control, address and data bus lines on bus structured designs. Enable/hold inputs to microprocessors. Enable and Read/write inputs to memory. Clock and preset/reset inputs to F/Fs, counters, shift registers, etc. Data select inputs to multiplexers and demultiplexers. Control lines on tri-state devices.

 Stem lines with high fanout. Global feedback path Redundant signal lines Outputs of devices with many inputs, e.g., multiplexers and parity generators. Outputs from state devices. Address, control, data buses

Initialization
Rule: Design circuits to be easily initialized Dont disable preset and clear lines.

Rule: Disable internal one shot.

Partitioning Counters and Shift Registers

Partitioning Counters and Shift Registers