CMOS

Presented by

Abhishek Bhagat

CMOS

Complementary Metal oxide Semiconductor

Why complementary
Complementary:

???

There are N-type and P-type transistors. N-type transistors use electrons as the current carriers.
P-type transistors use holes as the current carriers.

Complementary Symmetry (COS-MOS) :

Symmetrical pairs of p-type & n-type MOSFETS are used.

METAL OXIDE SEMICONDUCTOR

Metal: The gate of the transistor was made of aluminum metal in the early days, but is made of poly-silicon today (for the past 25 years or more).

Oxide :
Silicon dioxide is the material between the gate and the

channel

Semiconductor:
the semiconductor material is silicon, a type IV element

in the periodic chart. Each silicon atom bonds to four other silicon atoms in a tetrahedral crystal structure.

CMOS NFET and PFET Transistors

gate
oxide
N+

n N
source

n N+
drain

P substrate

N channel device

N channel device:
Built directly in the P substrate with N-doped source and drain

junctions and normally N-doped gate conductor

Requires positive voltage applied to gate and drain (with respect to source) for electrons to flow from source to drain (thought of as positive drain current)

gate
oxide
N+

P+ N
source N well

P+ N+
drain

P channel device

P channel device:
Built in an N-well (a deep N-type junction diffused into the P

substrate) with P-doped source and drain junctions and N or P-doped gate Requires negative voltage applied to gate and drain (with respect to source) for electrons to flow from drain to source (thought of as negative drain current)

N-FET and P-FET Devices as Switches

gate
oxide
N+

NFET Device:
positive voltage (1 or high)

n N
source

n N+

P substrate

gate source substrate

on gate relative to source turns device ON and allows drain positive current to flow from drain to source (switch closed) zero volts on gate (0 or low) turns device OFF (open circuit) Source (vs drain) is the most drain negative terminal

N-FET device schematic

gate
oxide

P+ N
source N well

P+ N+
drain

PFET Device:

gate

Negative voltage (0 or

source
substrate

drain

P-FET device schematic

low) on gate relative to source turns device ON and allows (negative) current to flow from drain to source (closes switch) Zero volts on gate relative to source (1 or high) turns device OFF (closes switch) source (vs drain) is the most positive terminal

Vdd

Simple CMOS Circuits: The Inverter Gate

PFET source

Inverter Schematic

P-FET
PFET drain

Vin

Vout NFET drain

N-FET
NFET source

Gnd

Inverter Symbol

Operation: The simplest complementary MOS (CMOS) is down (0 volts), NFET is If Vin circuit is the inverter: OFF and PFET is ON pulling NFET & PFET gates are connected Vout to Vdd (high input together as the = 1) If NFET upPFET drains areis Vin is & (at Vdd), NFET ON hard andtogether as the output connected PFET is OFF pulling Vout lowsources (0) NFET & PFET to Gnd are With Vin at 0to Gnd and dc connected or Vdd, no Vdd, current flows in inverter respectively. NFET substrate is normally connected to Gnd for all NFET devices in the circuit PFET well is normally connected to Vdd (most positive voltage in circuit) for all PFET devices

CMOS Circuits: The Transmission Gate

X gate Schematic
Vgc = Vg

P-FET
Vin
Vdd Gnd

Operation:
Vout

Circuit topology:

N-FET
Vg

X-gate Symbols

-s

in
s -s in s -s in s

out
out

out

N and P devices with When Vg is high (at Vdd) and Vgc is therefore low (at Gnd), the NFET and sources and drains PFET are both ON. parallel. upon connected in (Depending the devices source potentials, one may be ON more strongly than the Vg is the control signal other.) The switch is therefore for the N device; Vgc CLOSED and Vout will be the same (complement logic level as Vin. of Vg) is the When Vg is low (at Gnd) and Vgc is control signal for the P high (at Vdd), both devices are OFF. device. The switch is therefore OPEN and Vout will be independent of Vin (high Z connection).

CMOS Logic Circuits: Multiplexer

S0 S0 S1 S1 A P-FET N-FET B P-FET P-FET N-FET N-FET P-FET C P-FET N-FET Z

The

4-to-1 multiplexer shown at Multiplexers can be implemented

N-FET
P-FET D N-FET A B C D S0 S1 4-to-1 MUX

right: CMOS transmission gates or with orUsing combination of both.! with a Xmission gates, 12 Txs (plus 2 inverters for With CMOS gates, a 2-to-1 selects) requires 3 gates (2 multiplexer ANDs & 1 OR) having 12 Using CMOS logic, it Txs (plus inverter 3-input requires fourfor select)AND gatesXmission gates, a 2-to-1 With plus one 4-input OR multiplexer requires only 4 Txs gate for a total of 32 Txs (plus inverter for the select) (plus 2 inverters for the selects)

with standard CMOS logic gates

Uses of CMOS :
Integrated circuits.
Microprocessors Microcontrollers Static RAM etc.

Image sensors Data converters Highly integrated transcievers .

Microcontroller Microprocessor Image Sensor (CMOS sensor) Highly Integrated Transcievers Static RAM Data Converter