ARM/Thumb

2.3 ARM/THUMB
1. ARM
2. ARM
3. Thumb

1.ARM

ARM9

(1).

(2).

(3). (4).
(5).

(6).

(7).

(8).

(9).

(1).

MOV R1,R2

;R2R1
R2
0xAA
R1
0xAA
0x55
SUB R0,R1,R2 ;R1R2R0
MOV

R1,R2

(2).

)
MOV R0,#0xFF00

SUBS R0,R0,#1
;R01R0
R0 0xFF00
0x55

MOV R0,#0xFF000
;0xFF000R0
MOV R0,#0xFF00

(3).
ARM
22
1
3

R2 #3 0x01
0x08
MOV R0,R2,LSL
;R23R0
R0 ;R0=R28
0x55
0x08
ANDS R1,R1,R2,LSL
R3 ;R2R3R1
MOV R0,R2,LSL
#3
;R1

(4).

0x40000000
0xAA

LDR R1,[R2]

;R2
R2 0x40000000
R0
0xAA
0x55
;R1

SWP R1,R1,[R2] ;R1R2

LDR R0,[R2]
;

(5).

0x4000000C
0xAA
LDR R2,[R3,#0x0C] ;R3+0x0C
R3+0x0C
R3 0x40000000
;R2

R2
0xAA
0x55

STR R1,[R0,#-4]! ;R0=R0-4R1

;R0
LDR R2,[R3,#0x0C]

(6).
16

R6
0x??
0x04

0x4000000C
0x04

LDMIA
;R1
R4R1!,{R2-R7,R12}
0x??
0x03 0x40000008
0x03

;R2R7R12(R11)
R3
0x??
0x02 0x40000004
0x02

STMIA
;R2R7R12
R2R0!,{R2-R7,R12}
0x??
0x01 0x40000000

0x01

R1 0x40000000
0x40000010 ;R0;
LDMIA

;(R01)

R1!,{R2-R4,R6}

(7).

()()

(7).

0x12345678

SP

SP

0x12345678

(7).

SP
SP

0x12345678

0x12345678
SP
SP

0x12345678

(7).

LDMFASTMFA

LDMEASTMEA

LDMFDSTMFD

LDMEDSTMED

(8).

STMIA R0!,{R1-R7}

;R1R7

;
;
STMIB R0!,{R1-R7}

;R1R7

;
;

STMIB
STMFA

LDMIB
LDMED

STMIA
STMEA

LDMIA
LDMFD

LDMDB
LDMEA

STMDB
STMFD

LDMDA
LDMFA

STMDA
STMED

(7).

PC

BL

SUBRl SUBRl

...
SUBR1
MOV PC,R14

2. ARM
(1).
(2).
(3).ARM
(4). ARM
(5).
(6). ARM
(7).
(8).
(9).

2. ARM
ARM7TDMI(-S)
ARM
Thumb

ARM
ARMThumb

(1).
ARM
<opcode> {<cond>} {S}

<Rd> ,<Rn>{,<operand2>}

<>{}

opcode

cond

SCPSR
Rd

Rn1

operand22

LDR

R0[R1] R1AL

BEQ

D1

ADDS

SUBNES R1R1#0x10 (NE)R1 ; 0x10=>R1CPSR(S)

EQD1

R1R1#1 R1+1>R1CPSR
(S)

(1). 2
2operand2

#immed_8r
Rm
Rm,shift

(1).2
#immed_8r
88

10
00000000000000000000000000010010
0x00
0x00
0x00
0x12
8

00000100100000000000000000000000
0x04
0x80
0x00
0x00

(1).2
#immed_8r

0x3FC 0 0xF0000000 200

0xF0000001
MOV
R0#1
R01
0xlFE5110xFFFF0x1010
AND R1R2#0x0F R20x0FRl
0xF0000010
LDR R0[R1]#-4
R1 R1
R1- 4

(1).2
Rm

SUB

R1R1R2 R1-R2R1

MOV

PCR0

PC=R0

LDR R0[R1]-R2 Rl
R0R1 = R1 - R2

(1).2
Rm,shift

Rm

ASR #n

ROR #n

LSL #n

RRX

LSR #n

Type Rs

TypeRs
8

(1).2
LSL

LSR
ASR

0
ADD
SUB

ROR

RRX

R1R1R1LSL #3 R1=R19
R1R1R2LSR #2 R1=R1-R24

(2).
ARM
<opcode> {<cond>} {S}

<Rd> ,<Rn>{,<operand2>}

cond

ARMThumb
B
AL

0000

EQ

Z=1

0001

NE

Z=0

0010

CS/HS

C=1

0011

CC/LO

C=0

0100

MI

N=1

0101

PL

N=0

0110

VS

V=1

0111

VC

V=0

1000

HI

C=1,Z=0

1001

LS

C=0,Z=1

1010

GE

N=V

1011

LT

N!=V

1100

GT

Z=0,N=V

1101

LE

Z=1,N!=V

1110

AL

()

1111

NV

()

(3). ARM
ARMRISC
ARM
RAM
I/ORAM
IO/

(3). ARM

Rd[addressing]
addressing

LDR{cond}

LDRB Rd,addressing

Rd[addressing]
addressing

LDR{cond}B

LDRT Rd,addressing

Rd[addressing]
addressing

LDR{cond}T

LDRBT Rd, addressing

Rd[addressing]
addressing

LDR{cond}BT

LDRH Rd, addressing

Rd[addressing]
addressing

LDR{cond}H

LDRSB Rd, addressing

Rd[addressing]
addressing

LDR{cond}SB

LDRSH Rd, addressing

Rd[addressing]
addressing

LDR{cond}SH

LDR

Rd,addressing

(3). ARM

[addressing]Rd
addressing

STR{cond}

Rd,addressing

[addressing]Rd
addressing

STR{cond}B

Rd,addressing

[addressing]Rd

addressing

STR{cond}T

[addressing]Rd
/
addressing

STR{cond}BT

[addressing] Rd

addressing

STR{cond}H

STR

Rd, addressing

STRB
STRT

STRBT Rd,addressing
STRH

Rd,addressing

LDR/STR
LDRPC

(3). ARM
LDRSTR/
LDR
STR
T

LDR{cond}{T} Rd,<> ;Rd

T
STR{cond}{T} Rd,<> ;Rd
T

LDR{cond}B{T} Rd,<> ;Rd

STR{cond}B{T} Rd,<> ;Rd

(3). ARM
LDRSTR/
B1
0
P/

LL1
L0

I0
121

U/

Rd/
Rn

(3). ARM
LDRSTR/
LDR/STR

LDR R1[R0R2]
R1[R0R2LSL
#2]

LDR
R1[R0#0x12]
R0+R2
R0+0x12

R0+R24R1
R1
Rl(R0)
(R0R2)
LDR R1[R0-R2]
R1[R0-R2LSL
#2]R0LDR
R1[R0#
-0x12]
R0-R2
R0-0x12

R24R1(R0
R1(R0)
R1
R2)

(3). ARM
LDRSTR/
/
4

LDR

Rd,[Rn]

LDR

Rd,[Rn,#0x04]!

LDR
Rd[Rn# -0x04]

32
LDR
Rd,labe1

LDR

Rd,[Rn],#0x04

(3). ARM

LDRSTR/
1./32
LDR/STR
32
2.
//

LDR{cond}SB Rd,<> ;Rd

LDR{cond}SH Rd,<> ;Rd

LDR{cond}H Rd,<> ;Rd
STR{cond}H Rd,<> ;Rd

(3). ARM
LDRSTR/

LDRSB R1[R0R3] R0+R3R124

LDRSH R1[R9] R9R116

LDRH R6,[R2]#2R2R616
R2=R2+2 LDR/STR

STRH R1[Ro#2]! R1R0+22

R0=R0+2
LDRPC

(3). ARM
LDMSTM

LDM
STM
16

LDM{cond}<> Rn{!},reglist{^}
STM{cond}<> Rn{!},reglist{^}
LDMSTM

(3). ARM
/8

IA

FD

IB

ED

DA

FA

DB

EA

LDMIA/STMIA LDMIB/STMIB LDMDA/STMDA

LDMDB/STMDB
SP
STMFD/LDMFD STMED/LDMED STMFA/LDMFA
STMEA/LDMEA


Rn
RnR15

!Rn
reglist
{R1R2R6~R9}

^
LDMPC
SPSRCPSR

^
PC


Rn!,STM
,Rn,
Rn;Rn

[1:0]

LDMIA R0!{R3 - R9}R0

R3~R9R0
STMIA R1!{R3 - R9}R3R9R1
R1

STMFD
LDMFD

SP!{R0 - R7LR} R0R7LR

SP!{R0 - R7PC}

(3). ARM
SWP(Rn)
RdRm
SWP

SWP{cond}{B}

Rd,Rm,[Rn]

SWP
BB32
SWP
R1,R1,[R0]
;R1R0
RdRm
RmRnRn
SWPB
R1,R2,[R0]
;R0R1
RnRdRm
;(24)R2
;()

(4).ARM
3

ARM
S

CMPCMNTSTTEQ
S

(4). ARM

MOV

Rd,operand2

Rdoperand2

MOV{cond}{S}

MVN

Rd,operand2

Rd(~operand2)

MVN{cond}{S}

(4). ARM

MOV

Rd,operand2

Rdoperand2

MOV{cond}{S}

MVN

Rd,operand2

Rd(~operand2)

MVN{cond}{S}

MOV82#immed_8r
MOV
Rd

MOVS R3,R1,LSL #2
R3=R1<<2

MOV PC,LR MOV{cond}{S} PC=LR

Rd,operand2

(4). ARM

MOV

Rd,operand2

Rdoperand2

MOV{cond}{S}

MVN

Rd,operand2

Rd(~operand2)

MVN{cond}{S}

MVN82#immed_8r
MVN
operand2Rd
MVN
R1,#0xFF
R1=0xFFFFFF00

MVN
R1,R2
R2R1
MVN{cond}{S}

Rd,operand2

(4). ARM

ADD

Rd, Rn, operand2

RdRn+operand2

ADD{cond}{S}

SUB

Rd, Rn, operand2

RdRn-operand2

SUB{cond}{S}

RSB

Rd, Rn, operand2

Rdoperand2-Rn

RSB{cond}{S}

ADC

Rd, Rn, operand2

RdRn+operand2+Carry

ADC{cond}{S}

SBC

Rd, Rn, operand2

RdRn-operand2(NOT)Carry

SBC{cond}{S}

RSC

Rd, Rn, operand2

Rdoperand2-Rn(NOT)Carry

RSC{cond}{S}

(4). ARM

ADD

Rd, Rn, operand2

RdRn+operand2

ADD{cond}{S}

SUB

Rd, Rn, operand2

RdRn-operand2

SUB{cond}{S}

RSB

Rd, Rn, operand2

Rdoperand2-Rn

RSB{cond}{S}

ADC

Rd, Rn, operand2

RdRn+operand2+Carry

ADC{cond}{S}

SBC

Rd, Rn, operand2

RdRn-operand2(NOT)Carry

SBC{cond}{S}

RSC

Rd, Rn, operand2

Rdoperand2-Rn(NOT)Carry

RSC{cond}{S}

ADDoperand2Rn
Rd

ADDS ADD{cond}{S}
R1,R1,#1
;R1=R1+1
Rd,Rn,operand2
ADDS R3R1R2LSL #2 ; R3R1+R2<<2

(4). ARM

ADD

Rd, Rn, operand2

RdRn+operand2

ADD{cond}{S}

SUB

Rd, Rn, operand2

RdRn-operand2

SUB{cond}{S}

RSB

Rd, Rn, operand2

Rdoperand2-Rn

RSB{cond}{S}

ADC

Rd, Rn, operand2

RdRn+operand2+Carry

ADC{cond}{S}

SBC

Rd, Rn, operand2

RdRn-operand2(NOT)Carry

SBC{cond}{S}

RSC

Rd, Rn, operand2

Rdoperand2-Rn(NOT)Carry

RSC{cond}{S}

SUBRnoperand2

Rd
SUBS
R0,R0,#1
;R0=R0-1
SUB{cond}{S}
Rd,Rn,operand2
SUB R6R7#0x10
; R6R7-0x10

(4). ARM

ADD

Rd, Rn, operand2

RdRn+operand2

ADD{cond}{S}

SUB

Rd, Rn, operand2

RdRn-operand2

SUB{cond}{S}

RSB

Rd, Rn, operand2

Rdoperand2-Rn

RSB{cond}{S}

ADC

Rd, Rn, operand2

RdRn+operand2+Carry

ADC{cond}{S}

SBC

Rd, Rn, operand2

RdRn-operand2(NOT)Carry

SBC{cond}{S}

RSC

Rd, Rn, operand2

Rdoperand2-Rn(NOT)Carry

RSC{cond}{S}

RSBoperand2Rn

Rd
RSB R3,R1,#0xFF00
;R3=0xFF00-R1
RSBS RSB{cond}{S}
R1,R2,R2,LSL #2 Rd,Rn,operand2
;R1=(R2<<2)-R2=R23

(4). ARM

ADD

Rd, Rn, operand2

RdRn+operand2

ADD{cond}{S}

SUB

Rd, Rn, operand2

RdRn-operand2

SUB{cond}{S}

RSB

Rd, Rn, operand2

Rdoperand2-Rn

RSB{cond}{S}

ADC

Rd, Rn, operand2

RdRn+operand2+Carry

ADC{cond}{S}

SBC

Rd, Rn, operand2

RdRn-operand2(NOT)Carry

SBC{cond}{S}

RSC

Rd, Rn, operand2

Rdoperand2-Rn(NOT)Carry

RSC{cond}{S}

ADCoperand2Rn

CPSRCRd
ADDS R0,R0,R2
;ADC64

ADC R1,R1,R3
;(R1R0)(R1R0)+(R3
ADC{cond}{S}
Rd,Rn,operand2
R2)

(4). ARM

ADD

Rd, Rn, operand2

RdRn+operand2

ADD{cond}{S}

SUB

Rd, Rn, operand2

RdRn-operand2

SUB{cond}{S}

RSB

Rd, Rn, operand2

Rdoperand2-Rn

RSB{cond}{S}

ADC

Rd, Rn, operand2

RdRn+operand2+Carry

ADC{cond}{S}

SBC

Rd, Rn, operand2

RdRn-operand2(NOT)Carry

SBC{cond}{S}

RSC

Rd, Rn, operand2

Rdoperand2-Rn(NOT)Carry

RSC{cond}{S}

SBCRnoperand2
CPSRC(C

1)Rd
SUBS R0,R0,R2
;SBC64
SBC SBC{cond}{S}
R1,R1,R3 ; (R1R0)(R1R0)-(R3R2)
Rd,Rn,operand2

(4). ARM

ADD

Rd, Rn, operand2

RdRn+operand2

ADD{cond}{S}

SUB

Rd, Rn, operand2

RdRn-operand2

SUB{cond}{S}

RSB

Rd, Rn, operand2

Rdoperand2-Rn

RSB{cond}{S}

ADC

Rd, Rn, operand2

RdRn+operand2+Carry

ADC{cond}{S}

SBC

Rd, Rn, operand2

RdRn-operand2(NOT)Carry

SBC{cond}{S}

RSC

Rd, Rn, operand2

Rdoperand2-Rn(NOT)Carry

RSC{cond}{S}

RSCoperand2
RnCPSRCRd

RSBS R2,R0,#0

RSC RSC{cond}{S}
R3,R1,#0 ;RSC64
Rd,Rn,operand2

(4). ARM

AND

Rd, Rn, operand2

RdRn & operand2

AND{cond}{S}

ORR

Rd, Rn, operand2

RdRn | operand2

ORR{cond}{S}

EOR

Rd, Rn, operand2

RdRn ^ operand2

EOR{cond}{S}

BIC

Rd, Rn, operand2

BIC{cond}{S}

RdRn & (~operand2)

(4). ARM

AND

Rd, Rn, operand2

RdRn & operand2

AND{cond}{S}

ORR

Rd, Rn, operand2

RdRn | operand2

ORR{cond}{S}

EOR

Rd, Rn, operand2

RdRn ^ operand2

EOR{cond}{S}

BIC

Rd, Rn, operand2

BIC{cond}{S}

RdRn & (~operand2)

ANDoperand2
RnRd

ANDS R0,R0,#0x01 ;R0=R0&0x01

AND R2,R1,R3
AND{cond}{S} ;R2=R1&R3
Rd,Rn,operand2

(4). ARM

AND

Rd, Rn, operand2

RdRn & operand2

AND{cond}{S}

ORR

Rd, Rn, operand2

RdRn | operand2

ORR{cond}{S}

EOR

Rd, Rn, operand2

RdRn ^ operand2

EOR{cond}{S}

BIC

Rd, Rn, operand2

BIC{cond}{S}

RdRn & (~operand2)

ORRoperand2Rn
Rd
ORR{cond}{S}

Rd,Rn, operand2

ORR

R0,R0,#0x0F

;R041

(4). ARM

AND

Rd, Rn, operand2

RdRn & operand2

AND{cond}{S}

ORR

Rd, Rn, operand2

RdRn | operand2

ORR{cond}{S}

EOR

Rd, Rn, operand2

RdRn ^ operand2

EOR{cond}{S}

BIC

Rd, Rn, operand2

BIC{cond}{S}

RdRn & (~operand2)

EORoperand2Rn
Rd
EOR{cond}{S}

EOR
R1,R1,#0x0F
EORS
R0,R5,#0x01

Rd,Rn, operand2

;R14
; R50x01
;R0

(4). ARM

AND

Rd, Rn, operand2

RdRn & operand2

AND{cond}{S}

ORR

Rd, Rn, operand2

RdRn | operand2

ORR{cond}{S}

EOR

Rd, Rn, operand2

RdRn ^ operand2

EOR{cond}{S}

BIC

Rd, Rn, operand2

BIC{cond}{S}

RdRn & (~operand2)

BICRnoperand2
Rd
BIC{cond}{S}

BIC R1,R1,#0x0F

Rd,Rn, operand2

;R14

(4). ARM

CMP

Rn, operand2

N Z C VRnCMP{cond}
operand2

CMN

Rn, operand2

N Z C
CMN{cond}
VRn+operand2

TST

Rn, operand2

NZCVRn &
TST{cond}
operand2

TEQ

Rn, operand2

NZCVRn ^
TEQ{cond}
operand2

(4). ARM

CMP

Rn, operand2

N Z C VRnCMP{cond}
operand2

CMN

Rn, operand2

N Z C
CMN{cond}
VRn+operand2

TST

Rn, operand2

NZCVRn &
TST{cond}
operand2

TEQ

Rn, operand2

NZCVRn ^
TEQ{cond}
operand2

CMPRnoperand2
CPSR

CMP{cond}

CMP R1,#10

Rn, operand2

; R110

(4). ARM

CMP

Rn, operand2

N Z C VRnCMP{cond}

operand2

CMN

Rn, operand2

CMNADDS

N Z C
CMN{cond}
CMN
VRn+operand2

TST

Rn, operand2

NZCVRn &
TST{cond}

operand2

TEQ

Rn, operand2

NZCVRn ^
TEQ{cond}
operand2

CMNRnoperand2
CPSR

CMP{cond}
Rn, operand2

CMN R0#1 R0+1R01Z

1

(4). ARM

CMP

Rn, operand2

CMN

Rn, operand2

TST
TEQ

N Z C VRnCMP{cond}
operand2

N Z C
CMN{cond}
TSTANDS
VRn+operand2
TST
NZCVRn &
Rn, operand2

TST{cond}
operand2
TSTEQ
NZCVRn ^
Rn, operand2

TEQ{cond}
NE
operand2
0EQ
0
TSTRnoperand2
NE

CPSR

TST{cond}

TST R0,#0x01
TST R1,#0x0F

Rn, operand2

; R00
; R140

(4). ARM

CMP

Rn, operand2

CMN

Rn, operand2

TST

Rn, operand2

TEQ

Rn, operand2

N Z C VRn- CMP{cond}
operand2
TEQEORS
N Z C
TEQCMN{cond}
VRn+operand2

NZCVRn &
TEQ
TST{cond}
operand2
EQNE
NZCVRn ^

TEQ{cond}
operand2
EQ
NE

TEQRnoperand2
CPSR

TEQ R0,R1

TEQ{cond}

Rn, operand2

; R0R1 (VC)

(5).

ARM7TDMI
3232
32 32

32 3264/

(5).

MUL

Rd,Rm,Rs

32

RdRm*Rs (RdRm)

MUL{cond}{S}

MLA

Rd,Rm,Rs,Rn

32

RdRm*Rs+Rn (RdRm) MLA{cond}{S}

UMULL RdLo,RdHi,Rm,Rs 64

(RdLo,RdHi) Rm*Rs

UMULL{cond}{S}

UMLAL RdLo,RdHi,Rm,Rs 64

(RdLo,RdHi)
Rm*Rs+(RdLo,RdHi)

UMLAL{cond}{S}

SMULL RdLo,RdHi,Rm,Rs 64

(RdLo,RdHi) Rm*Rs

SMULL{cond}{S}

SMLAL RdLo,RdHi,Rm,Rs 64

(RdLo,RdHi)
Rm*Rs+(RdLo,RdHi)

SMLAL{cond}{S}

(5).

MUL

Rd,Rm,Rs

32

RdRm*Rs (RdRm)

MUL{cond}{S}

MLA

Rd,Rm,Rs,Rn

32

RdRm*Rs+Rn (RdRm) MLA{cond}{S}

UMULL RdLo,RdHi,Rm,Rs 64

(RdLo,RdHi) Rm*Rs

UMULL{cond}{S}

UMLAL RdLo,RdHi,Rm,Rs 64

(RdLo,RdHi)
Rm*Rs+(RdLo,RdHi)

UMLAL{cond}{S}

SMULL RdLo,RdHi,Rm,Rs 64

(RdLo,RdHi) Rm*Rs

SMULL{cond}{S}

SMLAL RdLo,RdHi,Rm,Rs 64

(RdLo,RdHi)
Rm*Rs+(RdLo,RdHi)

SMLAL{cond}{S}

32MULRmRs32
Rd

MUL{cond}{S}

Rd,Rm,Rs

MUL R1,R2,R3 ;R1=R2R3

MULS R0,R3,R7 ;R0=R3R7CPSRNZ

(5).

MUL

Rd,Rm,Rs

32

RdRm*Rs (RdRm)

MUL{cond}{S}

MLA

Rd,Rm,Rs,Rn

32

RdRm*Rs+Rn (RdRm) MLA{cond}{S}

UMULL RdLo,RdHi,Rm,Rs

64

(RdLo,RdHi) Rm*Rs

UMULL{cond}{S}

UMLAL RdLo,RdHi,Rm,Rs

64

(RdLo,RdHi)
Rm*Rs+(RdLo,RdHi)

UMLAL{cond}{S}

SMULL RdLo,RdHi,Rm,Rs

64

(RdLo,RdHi) Rm*Rs

SMULL{cond}{S}

SMLAL RdLo,RdHi,Rm,Rs

64

(RdLo,RdHi)
Rm*Rs+(RdLo,RdHi)

SMLAL{cond}{S}

32MLARmRs
332Rd

MLA

MLA{cond}{S}

R1,R2,R3,R0

Rd,Rm,Rs,Rn

; R1=R2R3+R0

(5).

MUL

Rd,Rm,Rs

32

RdRm*Rs (RdRm)

MUL{cond}{S}

MLA

Rd,Rm,Rs,Rn

32

RdRm*Rs+Rn (RdRm) MLA{cond}{S}

UMULL RdLo,RdHi,Rm,Rs

64

(RdLo,RdHi) Rm*Rs

UMULL{cond}{S}

UMLAL RdLo,RdHi,Rm,Rs

64

(RdLo,RdHi)
Rm*Rs+(RdLo,RdHi)

UMLAL{cond}{S}

SMULL RdLo,RdHi,Rm,Rs

64

(RdLo,RdHi) Rm*Rs

SMULL{cond}{S}

SMLAL RdLo,RdHi,Rm,Rs

64

(RdLo,RdHi)
Rm*Rs+(RdLo,RdHi)

SMLAL{cond}{S}

64UMULLRmRs

32RdLo32RdHi
UMLAL R0,R1,R5,R8 ;(R1R0)=R5R8+(R1R0)
UMULL{cond}{S}

RdLo,RdHi,Rm,Rs

(5).

MUL

Rd,Rm,Rs

32

RdRm*Rs (RdRm)

MUL{cond}{S}

MLA

Rd,Rm,Rs,Rn

32

RdRm*Rs+Rn (RdRm) MLA{cond}{S}

UMULL RdLo,RdHi,Rm,Rs

64

(RdLo,RdHi) Rm*Rs

UMULL{cond}{S}

UMLAL

RdLo,RdHi,Rm,Rs

64

(RdLo,RdHi)
Rm*Rs+(RdLo,RdHi)

UMLAL{cond}{S}

SMULL RdLo,RdHi,Rm,Rs

64

(RdLo,RdHi) Rm*Rs

SMULL{cond}{S}

SMLAL RdLo,RdHi,Rm,Rs

64

(RdLo,RdHi)
Rm*Rs+(RdLo,RdHi)

SMLAL{cond}{S}

64UMLALRmRs
64RdHiRdLo32RdLo32
RdHi

UMULL

UMLAL{cond}{S}

RdLo,RdHi,Rm,Rs

R0,R1,R5,R8 ; (R1R0)=R5R8

(5).

MUL

Rd,Rm,Rs

32

RdRm*Rs (RdRm)

MUL{cond}{S}

MLA

Rd,Rm,Rs,Rn

32

RdRm*Rs+Rn (RdRm) MLA{cond}{S}

UMULL RdLo,RdHi,Rm,Rs

64

(RdLo,RdHi) Rm*Rs

UMULL{cond}{S}

UMLAL RdLo,RdHi,Rm,Rs

64

(RdLo,RdHi)
Rm*Rs+(RdLo,RdHi)

UMLAL{cond}{S}

SMULL

RdLo,RdHi,Rm,Rs

64

(RdLo,RdHi) Rm*Rs

SMULL{cond}{S}

SMLAL RdLo,RdHi,Rm,Rs

64

(RdLo,RdHi)
Rm*Rs+(RdLo,RdHi)

SMLAL{cond}{S}

64SMULLRmRs
32RdLo32RdHi

SMLAL

SMULL{cond}{S}
RdLo,RdHi,Rm,Rs
R2,R3,R7,R6 ; (R3R2)=R7R6+(R3R2)

(5).

MUL

Rd,Rm,Rs

32

RdRm*Rs (RdRm)

MLA

Rd,Rm,Rs,Rn

32

RdRm*Rs+Rn (RdRm) MLA{cond}{S}

UMULL RdLo,RdHi,Rm,Rs

64

(RdLo,RdHi) Rm*Rs

UMULL{cond}{S}

UMLAL RdLo,RdHi,Rm,Rs

64

(RdLo,RdHi)
Rm*Rs+(RdLo,RdHi)

UMLAL{cond}{S}

SMULL RdLo,RdHi,Rm,Rs

64

(RdLo,RdHi) Rm*Rs

SMULL{cond}{S}

SMLAL

64

(RdLo,RdHi)
Rm*Rs+(RdLo,RdHi)

SMLAL{cond}{S}

RdLo,RdHi,Rm,Rs

MUL{cond}{S}

64SMLALRmRs
64RdHiRdLo32RdLo32
RdHi

SMULL

SMLAL{cond}{S}

R2,R3,R7,R6

RdLo,RdHi,Rm,Rs

; (R3R2)=R7R6

(6). ARM
ARM

PC
B
BL
BX

(6). ARM

label

PClabel

B{cond}

BL

label

LRPC-4PClabel

BL{cond}

BX

Rm

PClabel

BX{cond}

(6). ARM

label

PClabel

B{cond}

BL

label

LRPC-4PClabel

BL{cond}

BX

Rm

PClabel

BX{cond}

B32M
(ARM20)
B{cond}

Label

B
B

WAITA
0x1234

; WAITA
; 0x1234

(6). ARM

label

PClabel

B{cond}

BL

label

LRPC-4PClabel

BL{cond}

BX

Rm

PClabel
BL BX{cond}

32

BL
MBBL
R14(LR)

32M
BL{cond}

Label

BL

DELAY

; DELAY

(6). ARM

label

PClabel

B{cond}

BL

label

LRPC-4PClabel

BL{cond}

BX

Rm

PClabel

BX{cond}

BX
Rm32M
(ARM20)
BX{cond}

Rm

ADRL R0,ThumbFun+1 Thumb1

R0
BX
R0
R0
R0

(7).

CDP
coproc,opcode1,CRd,CRn,

CRm{,opcode2}

CDP{cond}

LDC{L}

coproc, CRd,<>

LDC{cond}{L}

STC{L}

coproc, CRd,<>

STC{cond}{L}

MCR
coproc,opcode1,Rd,CRn,
CRm{,opcode2}

ARM

MCR{cond}

MRC coproc,opcode1,Rd,CRn,
CRm{,opcode2}

ARM

MCR{cond}

(7).
ARMCDPARM

CDP{cond}

coproc,opcode1,CRd,CRn,CRm{,opcode2}

CDP

p7,0,c0,c2,c3,0

;70
;0

CDP

p6,1,c3,c4,c5

;61

(7).
LDC/STC

LDC{cond}{L}
coproc, CRd,<>

STC{cond}{L}
coproc, CRd,<>

(7).
LDC/STC

LDC

p5,c2,[R2,#4]

LDC

p6c2[R1]

STC

p5,c1,[R0]

STC

p5cl[R0#-0x04]

(7).
ARM
MCR/MRCMCRARM
MRC
ARM

MCR{cond}

MCRARM
coproc,opcode1,Rd,CRn,CRm{,opcode2}

MRC{cond}

MRC ARM
coproc,opcode1,Rd,CRn,CRm{,opcode2}

(7).
ARM
MCR/MRCMCRARM
MRC
ARM

MCR

p6,2,R7,c1,c2

MCR

p70R1c3c21

MRC
MRC

p5,2,R2,c3,c2
p70R0c1c21

(8).

ARM

SWI

immed_24

SWI{cond}

MRS

Rd,psr

RdpsrpsrCPSRSPSR

MRS{cond}

psr_fieldsRd/#immed_8rpsr
MSR{cond}
CPSRSPSR

MSR psr_fields,
Rd/#immed_8r

(8).
SWI
CPSRSPSRSWI
SWI
SWI:
SWI{cond}
immed_24

SWI 0
0
SWI 0xl23456
0xl23456

(8).
SWISWI

SWISWI24

24

MOV

R0,#34

;34

SWI

12

;12

24R0

MOV

R0,#12

;12

MOV

R1,#34

;34

SWI

(8).
SWISWI
SWIARMThumb
SPSR
SWILR
SWI
SWI_Handler

STMFD

SP!, {R0-R3, R12, LR}

MRS

R0, SPSR

; SPSR

STMFD

SP!, {R0}

; SPSR

TST

R0, #0x20

; T

LDRNEH R0, [LR,#-2]

; Thumb(16)

BICNE

R0, R0, #0xFF00

; Thumb8

LDREQ

R0, [LR,#-4]

; ARM(32)

BICEQ

R0, R0, #0xFF000000

; ARM24

...

LDMFD

SP!, {R0-R3, R12, PC}^ ; SWI

(8).

ARM
MRS{cond} Rdpsr
MRS
Rd
RdR15
psr CPSRSPSR

CPSRSPSR

MRS R1,CPSR CPSR,R1

MRS R2,SPSR SPSR,R2

(8).
ARMMRS
CPSRSPSRCPSR
SPSR

MRSMSRCPSRSPSR

IRQ/FIQ

MRSSPSR

(8).
ARMMSRCPSRSPSR
MRSCPSRSPSR--
/IRQ/FIQ
MSR1

MSR{cond}

psr_fields,#immed_8r

MSR2

MSR{cond}

psr_fields,Rm

MSR CPSRc#0xD3
MSR

CPSRcxsfR3

CPSR0]0xD3

CPSR=R3

MSRCPSRT
ARMThumbBX
(BX
)
MRSMSRCPSRSPSR

IRQ/FIQ

(9).
ARMARM
ARM
ARM
ARM

ADR
ADRL
LDR

NOP

(9).ADR
ADRPC
ADR
ADDSUBADR

ADR
ADR{cond}
register,expr

expr

LOOP
MOV R1#0xF0
-255255
ADR R2LOOP LOOPR2
-10201020
ADR
R3LOOP + 4
ADR
16

(9).ADRL
ADRLPC
ADR
ADRL

ADRL
ADRL{cond}
register,expr

expr
ADRL R0DATABUF
-64K64K
ADRL
R1DATABUF+80
DATABUF
-256K256K
SPACE 100 100
ADRL
16

(9). LDR
LDR32
LDR
MOVMVNMOVMVNLDR
LDR

LDR
LDR{cond}
register,=expr

PC

(9). LDR

LDR R0=0x12345678
320x12345678
LDR R0=DATA_BUF+60
DATA_BUF+60

LTORG

1.
4KB
2.ARMLDR
LDR=

(9).NOP
NOPARM,
MOV R0,R0

NOP
NOP

3. Thumb
ThumbARM
16
Thumb,
ThumbARM
Thumb
ARM
ARM

ThumbCODEl6
ARMBXThumb

ARMCODE32

Thumb
CPSRSPSR64
B

Thumb2

ThumbARM

1.
ARM

2.

ARM

R8~R15

MOVADDR8R15
CPSRALU

R8~R15Thumb
CPSRALU

3.
Thumb
R0~R7

4.

LDMSTMR0~R7

LDMIASTMIA

PUSHPOPR13

R0~R7,PUSH
R14,POPPC