5 Low-power CMOS Circuits

Circuit level choices

Different approaches and topologies Static versus dynamic Pass-gate versus normal CMOS Asynchronous versus synchronous

The coming thing in transistors

Polysilicon gate will be replaced by metal Silicon dioxide gate insulation will be replaced by material with higher dielectric constant Silicon substrate will be replaced by strained silicon Single gate will be replaced by double gate and basic transistor structure will change
3

Putting a strain in silicon to speed up transistors

The first step in making strained silicon is to replace some of the atoms in the top layer of the silicon wafer with germanium atoms. Because germanium atoms are bigger than silicon atoms, the distance between atoms in the silicongermanium layer increases. Next, a layer of silicon is grown on top of the silicon-germanium. The crystal structure in this top layer of silicon is strained as it stretches to line up with the silicongermanium layer below. 4

90-nm
Intel is charging into the nanoscale era with its new 90-nm manufacturing process. In this scale, the transistors will have gate lengths of only 50 nm. The silicon dioxide insulation, barely visible beneath the gate, is only about 5 atomic layers thick.
5

SIA (Semiconductor Industry Association)

According to the SIAs roadmap, high performance ICs will contain by 2016 more than 8.8 billion transistors in an are 280 nm2 Typical feature sizes, which are also referred to as linewidths, will shrink to 22 nm.

 Intel will take products to 32nm and beyond. Intel is looking at a variety of technologies including high-k/metal gate, 3-D transistors, and III-V materials, even carbon nanotubes, and semiconductor nanowires as highmobility materials for future high-speed and low-power transistor applications and future interconnect applications (SoC, NoC).
7

 To address the leakage problems that come with shrinking transistors, Intel has identified a new high-k material, to replace the transistor's silicon dioxide gate dielectric, and new metals to replace the polysilicon gate electrode of NMOS and PMOS transistors. These new materials, along with the right process recipe, reduce gate leakage to less than 4% of what it was for the previous process generation, while delivering record transistor performance.
8

 Intel is investigating 3-D transistors that have a gate that controls the flow of current from 3 sides.

5.2 Circuit Design Style

Fully complementary CMOS logic has excellent properties in many areas, such as ease of design, low-power dissipation, low sensitivity to noise and process variations, and scalability. However, the logic family suffers from lower performance, especially for large fanin gates.
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Differential Cascode Voltage Switch Logic

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5.2.2.1 Domino Logic

The output of a gate is sometimes precharged only to discharge in the evaluation phase. Therefore, the signal activity at the output can be high. Increased signal activity along with the extra load that the clock line has to drive is primarily responsible for high power dissipation in domino compared to static CMOS circuits.

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5.2.2.2 Differential Current Switch Logic (DCSL)

Here Q and Q discharge towards ground through T6, T7 and T10. The discharge of Q and Q is not symmetrical because the nMOS tree assures that one of the outputs, say Q, has a stronger path to ground. The cross-coupled inverter functions as a sense amplifier and boots the output voltage differential in the right direction.
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 The presence of transistors T5 and T8 is what differentiates this gate from other DCVS logic gates.

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 SPICE simulations show that internal node voltage swings for DCSL are of the order of 1 V with a supply voltage of 5 V. A completion signal may be generated by taking a NAND of the two outputs (precharged high). The power advantage is primarily because of the very low internal voltage swings.
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16

Lower clock load & Done signal

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Precharge low DCSL

The circuit enters the evaluate mode with the CLK going low. Since evaluation starts only after the outputs have crossed Vtn, the gate propagation delay degrades.

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Limiting the discharge voltage to Vtn lowers the power dissipation

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 Gate operation starts with CLK high, T9 on and nodes Q and Q equalized. Hence Q and Q discharges to a voltage that is Vtn or lower, through transistors T6 and T7.

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SSDL (sample set differential logic) CVSL (cascade voltage switch logic)

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ECDL (emitter coupled differential logic)

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5.3 Leakage current in deep submicrometer transistors

The off-state leakage in long-channel devices is dominated by drain-well and well-substrate reverse-bias pn junctions. For short-channel transistors, the off-state current is influenced by threshold voltage, channel physical dimensions, channel/surface doping profile, drain/source junction depths, gate oxide thickness, the supply voltage, the drain and the gate voltages.
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5.3.1.1 pn Reverse-Bias Current

A reverse-bias pn-junction leakage I1 has two main components: one is the minoritycarrier drift near the edge of the depletion region and the other is due to electron-hole pair generation in the depletion region of the reverse-bias junction.

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I1 PN Reverse-Bias Current I2 Weak Inversion I3 Drain-Induced Barrier-Lowering Effect I4 Gate-Induced Drain Leakage I5 Punchthrough I6 Narrow-Width Effect I7 Gate Oxide Tunneling I8 Hot-Carrier Injection
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Comparison of process technologies

m
1.0 0.8

VDD
5 5

Tox()
200 150

VT

Leff
0.80

Ioff (pA/ m) 0.00041

0.058

0.60

0.55

0.6
0.35 0.25 0.18

3.3
2.5 1.8 1.6

80
60 45 30

0.58
0.47 0.43 0.40

0.35
0.25 0.15 0.10

0.15
8.9 24 86
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Drain-induced barrier-lowering effect

Drain-induced barrier lowering (DIBL) occurs when the depletion region of the drain interacts with the source near the channel surface to lower the source potential barrier. The source then injects carriers into the channel surface without the gate playing a role. Higher surface and channel doping and shallow source/drain junction depths reduce the DISL leakage current mechanism. DIBL can be measured at constant VG as the change in ID for a change in VD. 31

Gate-Induced Drain Leakage

Gate induced drain leakage current arises in the high electric field under the gate/drain overlap region causing deep depletion. GIDL occurs at low VG and high VD bias and generates carriers into the substrate and drain from surface traps or band-to-band tunneling. Thinner tox, higher VDD, and LDD (lightly doped drain) structures enhance the electric-fielddependent GIDL.
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33

34

Punchthrough
Punchthrough occurs when the drain and source depletion region approach each other and electrically touch deep in the channel. Punchthrough is regarded as a subsurface version of DIBL.

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Minimum and maximum leakage current

circuit min
HSPICE GA 3-input 0.022 NAND Full adder 1.818 2-bit 1.842 Multiplier

max
Diff(%) HSPCIE GA 0.492 2.220 3.049 Diff(%)

0.021 4.5 1.909 5.0 1.894 2.8

0.485 1.4 2.281 2.7 3.055 0.2

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5.4 Deep Submicrometer Device Design Issues

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b1 long channel

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 In order to make the device work properly, dVth/dL cannot be too large. This will determine the minimum channel length Lmin.

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Drain-Induced Barrier Lowering

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5.5 Key to Minimizing shortchannel-effect (SCE)

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The small SCE of this transistor is because of the smaller depletion depth and junction depth.

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The effective junction depth and the depletion width are reduced to half of that of a bulk MOSFET.

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5.6 Low-Voltage Circuit Design Techniques

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5.6.3 Multiple Threshold Voltage

Different threshold voltage can be developed by multiple Vth implantation during the fabrication, by changing the substrate and source bias (body effect), by controlling the back gate of double-gate SOI devices.

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 When the leakage current is higher than a certain value, the Self-Sub-Bias will be triggered and will reduce the substrate bias of all the other nMOSFETs, which in turn will increase the threshold voltage and reduce the leakage current.

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MTCMOS Multithreshold CMOS uses both high- and lowthreshold voltage MOSFETs in a single chip and a sleep control scheme is introduced for efficient power management.

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The gate and substrate of the transistors are tied together.

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 Because of the body effect, the threshold voltage of MOSFETs can be changed dynamically during the different mode of operation. In the active mode, the circuit switches from low to high with a higher speed because of the low-Vth PMOS. In the standby mode, the static leakage current is decided by the subthreshold current of the high-Vth nMOS and is smaller. The supply voltage of DTMOS is limited by the diode built-in potential. The pn-junction diode between source and body should not be forward biased. So this technique is only suitable for ultra-low-voltage (0.6-V and below) circuits. 54

DGDT SOI MOSFETs combine the advantages of DTMOSs and Fully depleted (FD) SOI MOSFETs without the limitation of the supply voltage.

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 The back-gate oxide of DGDT SOI MOSFETs is thick enough to make the threshold voltage of the back gate larger than the supply voltage. The front gate is a conducting gate while the back gate acts as a controlling gate for the front gate.
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DGDT shows better subthreshold characteristics than FD

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The thinner the silicon layer thickness, the smaller is the threshold voltage. Thinning tob can improve the controllability of the back gate to the front gate, which increases the threshold voltage variation range.

58

Comparison of Ion/Ioff for different FD SOI MOSFETs and DGDT SOI MOSFETs
Vth
FDSOI NMOS 0.35

Ion/w at 1V (10-5 A/m)

6.12

Ioff/w at 1V (10-11 A/m)

1.33

Ion/ Ioff at 1V (106)

4.6

FDSOI PMOS (Vgbs = -1V)

FDSOI PMOS (Vgb = 0V) DGDT SOI NMOS DGST SOI PMOS

-0.13
-0.36

-5.54
-3.46

-6800
-0.735

0.0008
4.7

0.13-0.35 -0.13-0.36

10.02 -5.55

1.33 -0.735

7.53 7.55
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Good noise margin

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Switched source impedance

A switch source impedance is set at the source of transistor MN. Ss is turned on during the active mode and turned off during the standby mode.

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The sleep control scheme is achieved by a modified DTMOS. The body of high Vth is connected to the gates through a reverse-biased MOS Diode (MD)

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 In sleep mode (VGS = 0V), the drain-current of the variable high-Vth MOSFET equals that of the conventional MOSFET because the body voltage is equal to the source voltage of 0V. In active mode (VGS < 0V), the drain-current of the variable high-Vth MOSFET increases because the threshold voltage is reduced due to the bodyvoltage reduction. At the supply voltage of 0.5V, the variable highVth MOSFET increases the drain conductance to about three times that of the conventional 64 MOSFET.

5.6.4 Multiple Threshold CMOS Based on Path Criticality

Figure 5.41a is the original single-Vth circuit, where the supply voltage is 1 V and the threshold voltage is 0.2 V. Figure 5.41 b-d show the dual-Vth circuits with high threshold voltages of 0.25, 0.395, and 0.46 V, respectively. The low Vth is 0.2 Vdd.

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Active power dissipations of single-Vth and dual-Vth circuits at different frequencies.

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Optimal high threshold and static power saving

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5.8 Multiple Supply Voltages

Since power dissipation decreases quadratically with the scaling of supply voltage, while the delay is proportional to Vdd/(Vdd Vth)2, it is possible to use high supply voltage in the critical paths of a design to achieve the required performance while the off-critical paths of the design use lower supply voltage to achieve low-power dissipation.
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Data flow graph

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Lowering dynamic power

Reducing VDD has a quadratic effect
Has a negative effect on performance especially as VDD approaches 2VT Lowering CL
Improves performance as well Keep transistors minimum size (keeps intrinsic capacitance, gate and diffusion, small) Transistors should be sized only when CL is dominated by extrinsic capacitance

Reducing the switching activity, f 01 = P 01 * f

A function of signal statistics and clock rate Impacted by logic and architecture design decisions
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TSMC processes leakage and Vt

Vdd Tox CL018 CL018 CL018 CL018 CL015 CL013 ULP G LP HS HS HS 1.8 1.8 1.8 2 1.5 1.2 42 42 42 42 29 24

Idsat(A/m) 600/200 500/180 320/130 780/360 860/370 920/400

Ioff(pA/m) 20
Lgate m Vt 0.16 0.42

1.60
0.16 0.63 22

0.15
0.18 0.73 14

300
0.13 0.40 43

1,800
0.11 0.29 52

13,000
0.08 0.25 80
86

FET (GHz) 30

Basic principles of low power design

P = CLVDD 2f01 + tscVDDI peakf01 + VDDI leakage

Reduce switching (supply) voltage

Quadratic effect dramatic savings Negative effect on performance

Reduce capacitance Reduce switching frequency

Switching activity Clock rate

Reduce glitching Reduce short circuit currents (slope engineering) Reduce leakage currents

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Impacts of copper interconnect

Wire delay is proportional to its R (resistance) times C (capacitance), thus reducing C reduces signal delay, improves signal integrity and lowers power consumption Unfortunately as processes shrink, wires get shorter (reducing C) but they get closer together (increasing C) and narrower (increasing R). So RC wire delay increases and capacitive coupling gets worse. Copper has about 40% lower resistivity than aluminum, so copper wires can be thinner 88 (reducing C) without increasing R.

New technologies - SOI

Scaling of bulk CMOS below 0.13 micron is extremely difficult due to short-channel effects
As transistor channel length shrinks, parasitic factors become dominate
Loss of gate control (and transistor gain) High gate-overlap capacitance Subthreshold leakage Tunneling

Silicon on Insulator (SOI)

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