CMOS Fabrication

CMOS FABRICATION TECHNOLOGY

The simplified process sequence for the fabrication of CMOS integrated circuits on a p- type silicon substrate is shown.

The process starts with the creation of the n-well regions for pMOS transistors, by impurity implantation into the substrate.

Then, a thick oxide is grown in the regions surrounding the nMOS and pMOS active regions.
The thin gate oxide is subsequently grown on the surface through thermal oxidation. These steps are followed by the creation of n+ and p+ regions (source, drain and channel-stop implants). Finally the metallization is created (creation of metal interconnects).

Oxide Isolation -VSS n+ S p+

Metallization Metal
G D p+ G S n+ p-well +VDD p+

D n+

Field Oxide

Basic Processing Steps

The integrated circuit may be viewed as a set of patterned layers , a layer must be patterned before the next layer of material is applied on chip. The process used to transfer a pattern to a layer on the chip is called lithography.

The sequence starts with the thermal oxidation of the silicon surface, see (b).

The entire oxide surface is covered with a layer of photoresist, which is a light-sensitive, acid-resistant organic polymer, initially insoluble in the developing solution (c).

Thermal oxide

Thermal oxides can be created by the following reactions Si + 2H2O SiO2 + 2H2; wet oxidation Si + Air SiO2; native oxide

Basic Processing Steps

To selectively expose the photoresist, we have to cover some of the areas on the surface with a mask during exposure. Thus, when the structure with the mask on top is exposed to UV light, areas which are covered by the opaque features on the mask are shielded. The exposed areas of photoresist become soluble, no longer resistant to etching solvents.

Photo-Resist

PhotoResist normally comes in powder form, which is insensitive to light. It is reconstituted into liquid form by adding a solvent. The wafer is mounted on a turntable, spinning slowly, and the photoresist is discharged into its center. Centrifugal force spreads the resist outward across the wafer. The thickness that remains on the wafer is a function of the rate of wafer spin and the viscosity of the photoresist. Phase After the PR is applied, the wafer is heated (~160C) Interference gives to evaporate Photoresist Thickness the solvent, leaving a smooth solid coating. The type of photoresist which is initially insoluble and becomes soluble after exposure to UV light is called positive photoresist. Negative resist reacts the opposite way, with those areas which were NOT exposed to light being dissolved.

Photo-Resist Application

Basic Processing Steps

Following the UV exposure step, the exposed portions of the photoresist can be removed by a solvent.

Next, the silicon dioxide regions which are not covered by hardened photoresist can be etched away by using a chemical solvent (HF acid) (e).

At the end of this step, we obtain an oxide window that reaches down to the silicon surface (f).

The remaining (unexposed) photoresist can be stripped from the silicon dioxide surface by using another solvent, leaving the patterned silicon dioxide feature on the surface, see (g).

The fabrication of semiconductor devices requires several such pattern transfers to be performed on silicon dioxide, polysilicon, and metal.

Basic Processing Steps

Compare the unpatterned structure (top) and the patterned structure (bottom). It took 9 steps to make this simple hole:

1. 2. 3.

4.
5. 6. 7. 8.

9.

Oxidize silicon surface Deposit photoresist Anneal photoresist Mount mask above silicon Expose to UV light Develop photoresist Etch photoresist exposed to UV Etch SiO2 through photoresist hole Remove photoresist

Making a NMOS Device - 1

The process starts with the oxidation of the silicon substrate (a), in which a relatively thick silicon dioxide layer (5000A), also called field oxide, is created on the surface (b). Grow a passivation layer of SiO2 (silicon dioxide) over the entire wafer,to provide electrical stability by isolating the transistor surface from electrical and chemical conditions in the environment.

Then, the field oxide is selectively etched to expose the silicon surface on which the MOS transistor will be created (c).

Wet etching uses liquid solvents to remove materials eg, HF for SiO2 Dry etching uses gas to remove materials,can monitor reactants during process, determine automatically when etching is finished

Making a NMOS Device - 2

Following this step, the surface is covered with a thin, high-quality oxide layer , which will eventually form the gate oxide of the MOS transistor (d). On top of the thin oxide, a layer of polysilicon (polycrystalline silicon), is deposited (e). Polysilicon is used both as gate electrode material for MOS transistors and also as an interconnect medium in silicon integrated circuits.

After deposition, the polysilicon layer is patterned and etched to form the interconnects and the MOS transistor gates (f).

Making a NMOS Device - 3

The thin gate oxide not covered by polysilicon is also etched away, which exposes the bare silicon surface on which the source and drain junctions are to be formed (g).

The entire silicon surface is then doped with a high concentration of impurities, either through diffusion or ion implantation (n-type doping). (h)

The doping penetrates the exposed areas on the silicon surface, ultimately creating two n-type regions (source and drain junctions) in the p-type substrate. The impurity doping also penetrates the polysilicon on the surface, reducing its resistivity. Note the polysilicon gate, defines the precise location of the channel region and, hence, the location of the source and the drain regions. It is also called a self-aligned process.

Making a NMOS Device - 4

Once the source and drain regions are completed, the entire surface is again covered with an insulating layer of silicon dioxide (i).

The insulating oxide layer is then patterned in order to provide contact windows for the drain and source junctions (j).

Making a NMOS Device - 5

The surface is covered with evaporated aluminum which will form the interconnects (k).

Finally, the metal layer is patterned and etched, completing the interconnection of the MOS transistors on the surface (l).

Usually, a second (and third) layer of metallic interconnect can also be added on top of this structure by creating another insulating oxide layer, cutting contact (via) holes, depositing, and patterning the metal.

CMOS n-Well Process

The fabrication sequence of n-well CMOS integrated circuits.

The n-well CMOS process starts with a moderately doped p-type silicon substrate. Then, an initial thick field oxide layer is grown on the entire surface.

The first lithographic mask defines the nwell region. Donor atoms, usually phosphorus, are implanted through this window in the oxide.

Once the n-well is created, the active areas of the nMOS and pMOS transistors can be defined.

Following the creation of the n-well region, a thick field oxide is grown around the transistor active regions, and a thin gate oxide is grown on top of the active regions.

CMOS n-Well

The polysilicon layer is deposited using chemical vapor deposition (CVD) and patterned by dry plasma etching.

The created polysilicon lines will function as the gate electrodes of the nMOS and the pMOS transistors and their interconnects.

Also, the polysilicon gates act as self-aligned masks for the source and drain implantations that follow this step

CVD Chemical Reactions

Chemical Vapor Deposition, where reactive gases collide above the wafer, and chemical reaction products then fall onto the wafer creating a new layer.) SiH4(gas) + O2(gas) SiO2(solid) + 2H2 (gas) SiH4(gas) + H2(gas) +SiH2(gas) 2H2(gas) + PolySilicon (solid)

Continuous gas flow

Diffusion of reactants Boundary layer Deposited film Silicon substrate

CMOS n-Well
Using

a set of two masks, the n+ and p+ Source and Drain regions are implanted into the substrate and into the n- well, respectively.
The

ohmic contacts to the substrate and to the n-well are implanted in this process step.

Isolation layer (discussed later)

CMOS n-Well

An insulating silicon dioxide layer is deposited over the entire wafer using CVD .

The contacts are defined and etched away to expose the silicon or polysilicon contact windows.

These contact windows are necessary to complete the circuit interconnections using the metal layer, which is patterned in the next step.

CMOS n-Well

Metal is deposited over the entire chip surface using metal evaporation, and the metal lines are patterned through etching.

Since the metal connects two separate devices, it is called Local Interconnect. The connection of adjacent devices is often called LI-1, as being the lowest level of interconnection.

Interconnection Materials

Polysilicon interconnects are used to connect Gates and other shortdistance connections which have minimal currents. Polysilicon is a very stable material that rarely interacts with nearby materials. Metal interconnects have 3-5x the speed of polysilicon (electron mobility is higher) and less resistance. However, metals may react with nearby materials, and may have to be encapsulated using nitrides (e.g. Si3N4 or TiN) to prevent unwanted reactions, or partial erosion in subsequent etching procedures. This is expensive. In Upper Metallurgy (not local interconnects) metal is always used because processing is simple: only Metal + SiO2.

CMOS n-Well

The resulting cross-sectional view of the chip, showing one nMOS and one pMOS transistor (built-in n-well), the polysilicon and metal interconnections.

The final step is to deposit a full SiO2 passivation layer , for protection, over the chip, except for wire-bonding pad areas.

Latch-up is a very real, very important factor in circuit design that must be accounted for Due to (relatively) large current in substrate or n-well Create voltage drops across the resistive substrate/well Most common during large power/ground current spikes Turns on parasitic BJT devices, effectively shorting power & ground Often results in device failure with fused-open wire bonds or interconnects

Latch-Up

Latch-up

Hot carrier effects can also result in latch-up Latch-up very important for short channel devices Avoid latch-up by Including as many substrate/well contacts as possible Rule of thumb: one plugeach time a tx connects to the power rail Limiting the maximum supply current on the chip

Advanced CMOS Technologies Twin-Well MOS Technogy

For inexpensive and low-performance chips, one may use a heavily doped substrate and omit one well. The substrate should be doped to about 1016/cm3, with a resistivity of about 1 -cm. This allows simpler construction, with good Ground Potential distribution, but the devices are not optimal and there is a chance of latch-up if the voltages are pushed hard. For high-performance chips, one uses a low doped substrate, 1015/cm3, with a resistivity of about 10 -cm, and then constructs Two Wells at optimum doping levels ( Tubs ). Since the substrate is lightly doped, there is less chance for latch-up because of the high resistivity. This technology provides the basis for separate optimization of the nMOS and pMOS transistors, thus making it possible for threshold voltage, body effect and the channel transconductance of both types of transistors to be tuned independently

Advanced CMOS Technologies -Twin-Tub (Well) CMOS Process

The starting material is a n+ or p+ substrate, with a lightly doped epitaxial layer on top.

This epitaxial layer provides the actual substrate on which the n-well and the p-well are formed.

Since two independent doping steps are performed for the creation of the well regions, the dopant concentrations can be carefully optimized to produce the desired device characteristics.

Advanced CMOS Technologies

Silicon-on-Insulator (SOI) CMOS Process
Rather

than using silicon as the substrate material, an insulating substrate will improve process characteristics such as speed and latch-up susceptibility.
The

SOI CMOS technology allows the creation of independent, completely isolated nMOS and pMOS transistors virtually side-by-side on an insulating substrate.
The main advantages of this technology are : Higher integration density (because of the absence Complete avoidance of the latch-up Lower parasitic capacitances.

of well regions),

problem