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Fabrication
The process used that creates the devices/wires. Look at how to create:
Working transistors ndiff, pdiff, wells, poly, transistors, threshold adjust implants Wires contacts, metal1, via, metal2
Fabrication is pretty complex. Give a brief overview of the process, for background. Want to understand origin of layout rules / process parameters
The abstractions of the process for the designers (us). 2
Semiconductor Review
Create by doping a pure silicon crystal
Diffuse impurity into crystal lattice Changes the concentration of carriers
Electrons Holes
n+ n
p+ p
Buried contact
When there is no oxide between polysilicon and diffusion. Here two conducting materials contact one another. No transistor is formed
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Power Line
The 5v and 0v power line are implemented by in metal because of its very low resistance.
Contact Cut
In order to allow metal and diffusion to contact, metal is holed downed to the diffusion level and is called contact cut.
5V
Dep
Vout
5V
Dep
Vout
Enh
0V
8
5V
Dep
Vout
Vin
Enh
implant
0V
9
5V
Dep
Vout
Vin
Enh YES
Transistor Formed
0V
10
Dep
Contact cut
Vin
Vout
Enh
0V
11
Dep
P-type 0V
12
5V
Dep
P-type Vout
Vin Enh
P-type
0V
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Vout
P-type Mask-3: Define where Oxide is to be removed Vin Enh
P-type
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0V
Dep
Vout
Vin Enh
P-type
0V
15
5V
P-type
Dep
Mask-4 Defines area where PolySi is to be remain all gate areas Vin all PolySi to diffusion connection all PolySi interconnection
Vout
Enh
P-type
0V
16
5V
P-type
Dep
An unmask n+ diffusion now defines all source and drain regions Vin
Vout
Enh
P-type 0V
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5V
Dep
P-type
Wafer is covered with insulating Oxide which will insulate PolySi and diffusion from metal Vout
Vin
Enh
P-type 0V
Wafer is heated to provide smooth surface and to drive-in the n+ region
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5V
Dep
P-type Mask-5 define contact cut where Oxide is to be removed Vin Enh Vout
P-type 0V
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5V
P-type
Dep
Covered with Al
Vin
Vout
Enh
P-type 0V
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Dep
Vout
Enh
P-type
0V
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5V
Dep
P-type An Oxide overlay is grown to protect the surface Vin Enh Vout
P-type
0V
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5V
Dep P-type Vout Vin Mask-7 defines the area where overlay is etched away to allow the contact between Al of the input and output pads of the Chip and external circuitry. Enh
0V
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Scaling
Book: Lindas Book Page: 56-57
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Objectives
Evolution of smaller line widths, feature size and higher packing density. So need to understand the effects of scaling. Characteristics of Micro-electronic technology
Minimum feature size. Number of gates on a chip. Power dissipation. Maximum Operational frequency Die size Production cost.
25
Improved by shrinking the dimensions of transistors, interconnections and separation between features And by adjusting the doping levels and power voltages. In practice all dimensions are expressed in terms of . A value is assigned prior to manufacture. Advantage of this approach: design rules not become out dated.
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Scaling
The effects of scaling are most easily considered by assuming that all geometric dimensions (horizontal and Vertical) and voltages are reduced by a constant factor a.
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D new thickness D a
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L new length L a
Vp new supply vol tage V p a
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Saturation Current
I I (V gs Vt) 2 LD a
2
nW
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Current per transistor decreases by a factor a. a factor a2 more scaled devices can be placed on a similar sized chip. The current drawn from the supply increases by a factor a. The power supplied to a similar sized chip is unaltered by scaling
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Capacitor C
Circuit capacitances are reduced by factor a
LW
D
C a
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Gate delay
gate delay '
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Gate Power
gate power ' =
Vp I
Vp I 2 a
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Apart from the increase in current density on the chip, the other effects of reducing features and voltages are advantageous.
However, another unwanted effect arises when considering the delay down lines interconnecting gates. Here, the length does not scale as the chip is assumed to be of similar area. Hence, the line length is constant.
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Line Capacitance
C i'=
LW '
D'
= Ci
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Line Resistance
Ri
L W 'T '
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The delay down an interconnection line is proportional to Ri ' C ' i and thus scale up by a factor a2.
Delays in polysilicon and diffusion becomes unacceptably large and delay down metal lines is no longer negligible. This suggest that it will not be sensible to scale all the features an identical factor.
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