Integrated Circuits

A Design Perspective
Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic

Manufacturing Process
July 30, 2002
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CMOS Process

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A Modern CMOS Process

gate-oxide TiSi2 AlCu SiO2 Tungsten
poly
p-well n-well

SiO2 p+

n+

p-epi p+

Dual-Well Trench-Isolated CMOS Process

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Circuit Under Design

VDD M2 M4 Vin Vout Vout2 VDD

M1

M3

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Its Layout View

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The Manufacturing Process

For a great tour through the IC manufacturing process and its different steps, check http://www.fullman.com/semiconductors/semiconductors.html

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Photo-Lithographic Process
optical mask oxidation

photoresist removal (ashing)

photoresist coating stepper exposure

Typical operations in a single photolithographic cycle (from [Fullman]). photoresist development acid etch process step spin, rinse, dry

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Patterning of SiO2
Chemical or plasma etch Si-substrate (a) Silicon base material Photoresist SiO 2 Si-substrate (b) After oxidation and deposition of negative photoresist UV-light Patterned optical mask Exposed resist Si-substrate (c) Stepper exposure Si-substrate (f) Final result after removal of resist Si-substrate (e) After etching Hardened resist SiO 2 Si-substrate

(d) After development and etching of resist, chemical or plasma etch of SiO 2 Hardened resist SiO 2

SiO 2

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CMOS Process at a Glance

Define active areas Etch and fill trenches

Implant well regions

Deposit and pattern polysilicon layer

Implant source and drain regions and substrate contacts

Create contact and via windows Deposit and pattern metal layers
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CMOS Process WalkThrough

p-epi + p SiN 34 p-epi + p SiO 2 (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer) (a) Base material: p+ substrate with p-epi layer

p+

(c) After plasma etch of insulating trenches using the inverse of the active area mask

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CMOS Process WalkThrough

SiO 2 (d) After trench filling, CMP planarization, and removal of sacrificial nitride

(e) After n-well and V adjust implants Tp

(f) After p-well and V adjust implants Tn

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CMOS Process WalkThrough

poly(silicon) (g) After polysilicon deposition and etch

n +

+ p (h) After n+ source/drain and p source/drain implants. These + steps also dope the polysilicon.

SiO 2 (i) After deposition of SiO 2 insulator and contact hole etch.

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CMOS Process WalkThrough

Al (j) After deposition and patterning of first Al layer.

Al

SiO 2 (k) After deposition of SiO insulator, etching of vias, 2 deposition and patterning of second layer of Al.

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Advanced Metallization

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Advanced Metallization

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Design Rules

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3D Perspective
Polysilicon Aluminum

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Design Rules
Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules)

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CMOS Process Layers

Layer Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Color Yellow Green Green Red Blue Magenta Black Black Black Representation

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Layers in 0.25 m CMOS process

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Intra-Layer Design Rules

Same Potential 0 or 6 10 3 Active 3 2 Select Contact or Via Hole 2 2 Metal2 3 Metal1 3 4 Different Potential 9 Polysilicon 2 3 2 Well

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Transistor Layout
Transistor 1

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Vias and Contacts

2 Via 1 1 5 Metal to 1 Active Contact Metal to Poly Contact 3 2 4

2 2

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Select Layer
2 3 2 1 3 3 Select

Substrate

Well

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CMOS Inverter Layout

GND In VD D A A

Out (a) Layout

A p-substrate n
+

A n p
+

Field Oxide

(b) Cross-Section along A-A

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Layout Editor

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Design Rule Checker

poly_not_fet to all_diff minimum spacing = 0.14 um.

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Sticks Diagram
V DD In 3 Out
Dimensionless layout entities Only topology is important Final layout generated by compaction program

1
GND
Stick diagram of inverter
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Packagin g

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Packaging Requirements
Electrical:

Low parasitics Mechanical: Reliable and robust Thermal: Efficient heat removal Economical: Cheap

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Bonding Techniques
Wire Bonding

Substrate Die Pad

Lead Frame

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Tape-Automated Bonding (TAB)

Sprocket hole Film + Pattern Test pads Lead frame Die Solder Bump

Substrate (b) Die attachment using solder bumps.

Polymer film (a) Polymer Tape with imprinted wiring pattern.

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Flip-Chip Bonding
Die Solder bumps Interconnect layers

Substrate

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Package-to-Board Interconnect

(a) Through-Hole Mounting

(b) Surface Mount

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Package Types

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Package Parameters

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Multi-Chip Modules

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