Chapter 4 Input Output Systems

Click to edit Master subtitle style

6/6/12

Input / Output Problems

Why peripherals are connected directly to the system bus

Wide variety of peripherals Delivering different data formats At different speeds either slow or fast Interface to processor and Memory Interface to one or more peripherals

Need I/O modules and its functions

6/6/12

22

Model of I/O Module

6/6/12

33

External Devices

Human readable - user

Screen, printer, keyboard magnetic disk, tape, sensors and actuators Modem Network Interface Card (NIC)

Machine readable - equipment

Communication remote places

6/6/12

44

External Device Block Diagram

6/6/12

55

I/O Module Functions

Control & Timing CPU Communication Device Communication Data Buffering Error Detection

6/6/12

66

Control And Timing

To coordinate the flow of traffic between CPU and devices Steps

CPU checks I/O module device status I/O module returns status If ready, CPU requests data transfer I/O module gets data from device I/O module transfers data to CPU

6/6/12

77

Processor Communication

I/O module has to communicate with processor also Command decoding Data Status reporting Address recognition Must communicate with device also Commands Status information Data
88

Device communication:

6/6/12

Data buffering

Buffered in I/O module and then sent to peripheral devices In opposite direction also same Report errors to the processor. Mechanical and electrical malfunctions (paper jam, bad disk number) Changes in bit pattern Parity bits

Error detection

6/6/12

99

I/O Module Block Diagram

6/6/12

1010

I/O Module Decisions

Hide device properties to CPU Support multiple or single device Control device functions or leave for CPU

6/6/12

1111

Input Output Techniques

Programmed Interrupt driven Direct Memory Access (DMA)

6/6/12

1212

Programmed I/O

CPU has direct control over I/O

Sensing status Read/write commands Transferring data

CPU waits for I/O module to complete operation Wastes CPU time

6/6/12

1313

Working

CPU issues command to I/O module I/O module performs operation I/O module sets status bits CPU checks status bits periodically I/O module does not inform CPU directly or interrupt it

6/6/12

1414

I/O Commands

While executing CPU issues

Address of the I/O module External device An I/O command. Control - activate or telling module what to do Test - check status

Commands

e.g. powered on or not, Error.

Read to obtain a data from peripheral Write take data to peripheral

1515

6/6/12

6/6/12

1616

Addressing I/O Devices

Each device given unique identifier CPU commands contain identifier (address)

6/6/12

1717

I/O Mapping

Memory mapped I/O

Devices and memory share an address space Treats data and status registers as memory locations No special commands for I/O

Same instructions for both data and memory

Isolated I/O

Separate address spaces Need I/O or memory select lines Special commands for I/O Limited set

6/6/12

1818

Memory Mapped I/O

6/6/12

1919

Isolated I/O

6/6/12

2020

Interrupt Driven I/O

Overcomes CPU waiting No repeated CPU checking of device I/O module interrupts when ready

6/6/12

2121

Basic Operation

CPU issues read command I/O module gets data from peripheral while CPU does other work I/O module interrupts CPU CPU requests data I/O module transfers data

6/6/12

2222

6/6/12

2323

Simple Interrupt Processing

6/6/12

2424

6/6/12

2525

Design Issues

How the processor identifies that which module issued the interrupt? How does the processor deals with multiple interrupts?

6/6/12

2626

Identifying Interrupting Module Different line for each module

Limits number of devices CPU asks each module in turn Slow Interrupt Acknowledge sent down a chain Requested module responds by placing a word on data bus containing an identifier - vector Vectored interrupt
2727

Software poll

Daisy Chain or Hardware poll

6/6/12

Bus arbitration

Uses vectored interrupt Module must claim the bus before it can raise interrupt One module can do Processor detects interrupt and acknowledges, the module places its vector

6/6/12

2828

Based on priority Multiple lines

Multiple Interrupts

Each line has its priority Polling determines priority Order of modules only current master can interrupt

Software polling

Daisy chain

Bus arbitration

6/6/12

2929

89C59A interrupt controller

80x86 has one interrupt line only 80x86 based systems use 82C59A interrupt controller 82C59A has 8 interrupt lines

6/6/12

3030

Accepts interrupts from attached modules Determines priority Signals processor (raises INTR line) CPU Acknowledges (INTA line) Puts correct vector on data bus CPU processes interrupt

Sequence of Events 82C59A

6/6/12

3131

6/6/12

3232

Interrupt modes

Fully nested

Ordered in priority from 0(IR0) to 7(IR7) Equal priority, then serviced one after other Take interrupts from certain devices only

Rotating

Special mask

6/6/12

3333

Intel 82C55A Programmable Peripheral Interface

6/6/12

3434

Keyboard/Display Interfaces to 82C55A

6/6/12

3535

Interrupt driven and programmed I/O require active CPU intervention

Direct Memory Access

Transfer rate is limited Number of instructions must be executed for single I/O transfer Large volumes of data can be moved easily

DMA

DMA controller takes over from CPU for I/O

6/6/12

3636

DMA Block Diagram

6/6/12

3737

CPU tells DMA controller:

DMA Operation

Read/Write Device address Starting address of memory block for data Amount of data to be transferred

CPU carries on with other work DMA controller deals with transfer

Without going to the processors

DMA controller sends interrupt when finished Processor is involved only at the starting and at end of transfer 6/6/12 3838

DMA controller takes over bus for a cycle Transfer of one word of data and returns control to the processor Not an interrupt

DMA Transfer - Cycle Stealing

CPU does not switch context

Slows down CPU but not as much as CPU doing transfer

6/6/12

3939

DMA and Interrupt Breakpoints during an Instruction Cycle

6/6/12

4040

DMA Configurations (1)

Single Bus, Detached DMA controller Each transfer uses bus twice

I/O to DMA then DMA to memory

CPU is suspended twice

6/6/12

4141

DMA Configurations (2)

Single Bus, Integrated DMA controller DMA may support more than one device Each transfer uses bus once

6/6/12

DMA to memory

4242

DMA Configurations (3)

Separate I/O Bus Each transfer uses bus once

DMA to memory

CPU is suspended once

4343

6/6/12

Intel 8237A DMA Controller

Interfaces to 80x86 family and DRAM DMA module needs buses it sends HOLD signal to processor Processor responds HLDA then DMA can use buses Ex. transfer data from memory to disk
Device requests by pulling DREQ (DMA request) high DMA puts high on HRQ (hold request), CPU finishes present bus cycle and puts high on HDLA (hold acknowledge). HOLD remains active for duration of DMA 4444 6/6/12 DMA activates DACK (DMA acknowledge),

8237 DMA Usage of Systems Bus

6/6/12

4545

DMA starts transfer DMA deactivates HRQ, giving bus back to CPU

While DMA using buses processor idle and while Processor using bus, DMA idle

Known as fly-by DMA controller Data does not pass through and is not stored in DMA chip

DMA only between I/O port and memory Not between two I/O ports or two memory locations
6/6/12 4646

I/O Channels - Evolution

CPU directly controls the peripherals I/O module programmed I/o I/O module interrupt DMA Processor on its own CPU initiates I/O module with memory

6/6/12

4747

I/O Channel Architecture

6/6/12

4848

6/6/12

Byte multiplexor low speed devices Block multiplexor high speed devices
4949